* [PATCH v3 1/3] target/riscv: add CPU QOM header
2023-04-11 18:35 [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Daniel Henrique Barboza
@ 2023-04-11 18:35 ` Daniel Henrique Barboza
2023-04-17 2:55 ` Alistair Francis
2023-04-11 18:35 ` [PATCH v3 2/3] target/riscv: add query-cpy-definitions support Daniel Henrique Barboza
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-04-11 18:35 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, richard.henderson, Daniel Henrique Barboza
QMP CPU commands are usually implemented by a separated file,
<arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
This file uses a CPU QOM header with basic QOM declarations for the
arch.
We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
but first we need a cpu-qom.h header with the definitions of
TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 46 +--------------------------
2 files changed, 71 insertions(+), 45 deletions(-)
create mode 100644 target/riscv/cpu-qom.h
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
new file mode 100644
index 0000000000..b9318e0783
--- /dev/null
+++ b/target/riscv/cpu-qom.h
@@ -0,0 +1,70 @@
+/*
+ * QEMU RISC-V CPU QOM header
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_CPU_QOM_H
+#define RISCV_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_CPU "riscv-cpu"
+
+#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
+#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
+
+#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
+#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
+#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
+#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
+#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
+#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
+#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
+
+#if defined(TARGET_RISCV32)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
+#elif defined(TARGET_RISCV64)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#endif
+
+typedef struct CPUArchState CPURISCVState;
+
+OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
+
+/**
+ * RISCVCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RISCV CPU model.
+ */
+struct RISCVCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86e08d10da..fa2655306d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -28,6 +28,7 @@
#include "qemu/int128.h"
#include "cpu_bits.h"
#include "qapi/qapi-types-common.h"
+#include "cpu-qom.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -37,32 +38,6 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 1
-#define TYPE_RISCV_CPU "riscv-cpu"
-
-#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
-#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
-#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
-
-#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
-#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
-#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
-#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
-#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
-#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
-#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
-#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
-#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
-#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
-#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
-#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
-#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
-
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
-#endif
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
@@ -101,8 +76,6 @@ enum {
#define MAX_RISCV_PMPS (16)
-typedef struct CPUArchState CPURISCVState;
-
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
#include "debug.h"
@@ -387,23 +360,6 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
-
-/*
- * RISCVCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RISCV CPU model.
- */
-struct RISCVCPUClass {
- /* < private > */
- CPUClass parent_class;
- /* < public > */
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
/*
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
* satp mode that is supported. It may be chosen by the user and must respect
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 1/3] target/riscv: add CPU QOM header
2023-04-11 18:35 ` [PATCH v3 1/3] target/riscv: add CPU QOM header Daniel Henrique Barboza
@ 2023-04-17 2:55 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2023-04-17 2:55 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> QMP CPU commands are usually implemented by a separated file,
> <arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
> This file uses a CPU QOM header with basic QOM declarations for the
> arch.
>
> We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
> but first we need a cpu-qom.h header with the definitions of
> TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
> cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++
> target/riscv/cpu.h | 46 +--------------------------
> 2 files changed, 71 insertions(+), 45 deletions(-)
> create mode 100644 target/riscv/cpu-qom.h
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> new file mode 100644
> index 0000000000..b9318e0783
> --- /dev/null
> +++ b/target/riscv/cpu-qom.h
> @@ -0,0 +1,70 @@
> +/*
> + * QEMU RISC-V CPU QOM header
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_CPU_QOM_H
> +#define RISCV_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_CPU "riscv-cpu"
> +
> +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
> +
> +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
> +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
> +
> +#if defined(TARGET_RISCV32)
> +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
> +#elif defined(TARGET_RISCV64)
> +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
> +#endif
> +
> +typedef struct CPUArchState CPURISCVState;
> +
> +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> +
> +/**
> + * RISCVCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A RISCV CPU model.
> + */
> +struct RISCVCPUClass {
> + /*< private >*/
> + CPUClass parent_class;
> + /*< public >*/
> + DeviceRealize parent_realize;
> + ResettablePhases parent_phases;
> +};
> +
> +#endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 86e08d10da..fa2655306d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -28,6 +28,7 @@
> #include "qemu/int128.h"
> #include "cpu_bits.h"
> #include "qapi/qapi-types-common.h"
> +#include "cpu-qom.h"
>
> #define TCG_GUEST_DEFAULT_MO 0
>
> @@ -37,32 +38,6 @@
> */
> #define TARGET_INSN_START_EXTRA_WORDS 1
>
> -#define TYPE_RISCV_CPU "riscv-cpu"
> -
> -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
> -
> -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> -#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> -#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> -#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> -#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> -#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> -#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> -#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> -#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> -#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> -#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> -#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
> -#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
> -
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
> -#endif
> -
> #define RV(x) ((target_ulong)1 << (x - 'A'))
>
> /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
> @@ -101,8 +76,6 @@ enum {
>
> #define MAX_RISCV_PMPS (16)
>
> -typedef struct CPUArchState CPURISCVState;
> -
> #if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> #include "debug.h"
> @@ -387,23 +360,6 @@ struct CPUArchState {
> uint64_t kvm_timer_frequency;
> };
>
> -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> -
> -/*
> - * RISCVCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A RISCV CPU model.
> - */
> -struct RISCVCPUClass {
> - /* < private > */
> - CPUClass parent_class;
> - /* < public > */
> - DeviceRealize parent_realize;
> - ResettablePhases parent_phases;
> -};
> -
> /*
> * map is a 16-bit bitmap: the most significant set bit in map is the maximum
> * satp mode that is supported. It may be chosen by the user and must respect
> --
> 2.39.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] target/riscv: add query-cpy-definitions support
2023-04-11 18:35 [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Daniel Henrique Barboza
2023-04-11 18:35 ` [PATCH v3 1/3] target/riscv: add CPU QOM header Daniel Henrique Barboza
@ 2023-04-11 18:35 ` Daniel Henrique Barboza
2023-04-17 2:56 ` Alistair Francis
2023-04-11 18:35 ` [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Daniel Henrique Barboza
2023-04-17 2:58 ` [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Alistair Francis
3 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-04-11 18:35 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, richard.henderson, Daniel Henrique Barboza
This command is used by tooling like libvirt to retrieve a list of
supported CPUs. Each entry returns a CpuDefinitionInfo object that
contains more information about each CPU.
This initial support includes only the name of the CPU and its typename.
Here's what the command produces for the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}]
}
Next patch will introduce a way to tell whether a given CPU is static or
not.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
qapi/machine-target.json | 6 ++--
target/riscv/meson.build | 3 +-
target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++
3 files changed, 59 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/riscv-qmp-cmds.c
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index 2e267fa458..f3a3de6648 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -324,7 +324,8 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
- 'TARGET_LOONGARCH64' ] } }
+ 'TARGET_LOONGARCH64',
+ 'TARGET_RISCV' ] } }
##
# @query-cpu-definitions:
@@ -341,4 +342,5 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
- 'TARGET_LOONGARCH64' ] } }
+ 'TARGET_LOONGARCH64',
+ 'TARGET_RISCV' ] } }
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 5b7f813a3e..e1ff6d9b95 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files(
'monitor.c',
'machine.c',
'pmu.c',
- 'time_helper.c'
+ 'time_helper.c',
+ 'riscv-qmp-cmds.c',
))
target_arch += {'riscv': riscv_ss}
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
new file mode 100644
index 0000000000..128677add9
--- /dev/null
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -0,0 +1,53 @@
+/*
+ * QEMU CPU QMP commands for RISC-V
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qapi/qapi-commands-machine-target.h"
+#include "cpu-qom.h"
+
+static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
+ const char *typename = object_class_get_name(oc);
+
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_RISCV_CPU));
+ info->q_typename = g_strdup(typename);
+
+ QAPI_LIST_PREPEND(*cpu_list, info);
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list = object_class_get_list(TYPE_RISCV_CPU, false);
+
+ g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/3] target/riscv: add query-cpy-definitions support
2023-04-11 18:35 ` [PATCH v3 2/3] target/riscv: add query-cpy-definitions support Daniel Henrique Barboza
@ 2023-04-17 2:56 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2023-04-17 2:56 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
On Wed, Apr 12, 2023 at 4:37 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This command is used by tooling like libvirt to retrieve a list of
> supported CPUs. Each entry returns a CpuDefinitionInfo object that
> contains more information about each CPU.
>
> This initial support includes only the name of the CPU and its typename.
> Here's what the command produces for the riscv64 target:
>
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
> {"QMP": {"version": (...)}
> {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
> {"return": {}}
> {"execute": "query-cpu-definitions"}
> {"return": [
> {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false},
> {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
> {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
> {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false},
> {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}]
> }
>
> Next patch will introduce a way to tell whether a given CPU is static or
> not.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> qapi/machine-target.json | 6 ++--
> target/riscv/meson.build | 3 +-
> target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+), 3 deletions(-)
> create mode 100644 target/riscv/riscv-qmp-cmds.c
>
> diff --git a/qapi/machine-target.json b/qapi/machine-target.json
> index 2e267fa458..f3a3de6648 100644
> --- a/qapi/machine-target.json
> +++ b/qapi/machine-target.json
> @@ -324,7 +324,8 @@
> 'TARGET_I386',
> 'TARGET_S390X',
> 'TARGET_MIPS',
> - 'TARGET_LOONGARCH64' ] } }
> + 'TARGET_LOONGARCH64',
> + 'TARGET_RISCV' ] } }
>
> ##
> # @query-cpu-definitions:
> @@ -341,4 +342,5 @@
> 'TARGET_I386',
> 'TARGET_S390X',
> 'TARGET_MIPS',
> - 'TARGET_LOONGARCH64' ] } }
> + 'TARGET_LOONGARCH64',
> + 'TARGET_RISCV' ] } }
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 5b7f813a3e..e1ff6d9b95 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files(
> 'monitor.c',
> 'machine.c',
> 'pmu.c',
> - 'time_helper.c'
> + 'time_helper.c',
> + 'riscv-qmp-cmds.c',
> ))
>
> target_arch += {'riscv': riscv_ss}
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> new file mode 100644
> index 0000000000..128677add9
> --- /dev/null
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -0,0 +1,53 @@
> +/*
> + * QEMU CPU QMP commands for RISC-V
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qapi/qapi-commands-machine-target.h"
> +#include "cpu-qom.h"
> +
> +static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
> +{
> + ObjectClass *oc = data;
> + CpuDefinitionInfoList **cpu_list = user_data;
> + CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
> + const char *typename = object_class_get_name(oc);
> +
> + info->name = g_strndup(typename,
> + strlen(typename) - strlen("-" TYPE_RISCV_CPU));
> + info->q_typename = g_strdup(typename);
> +
> + QAPI_LIST_PREPEND(*cpu_list, info);
> +}
> +
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
> +{
> + CpuDefinitionInfoList *cpu_list = NULL;
> + GSList *list = object_class_get_list(TYPE_RISCV_CPU, false);
> +
> + g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list);
> + g_slist_free(list);
> +
> + return cpu_list;
> +}
> --
> 2.39.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-04-11 18:35 [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Daniel Henrique Barboza
2023-04-11 18:35 ` [PATCH v3 1/3] target/riscv: add CPU QOM header Daniel Henrique Barboza
2023-04-11 18:35 ` [PATCH v3 2/3] target/riscv: add query-cpy-definitions support Daniel Henrique Barboza
@ 2023-04-11 18:35 ` Daniel Henrique Barboza
2023-04-12 10:18 ` Richard Henderson
2023-04-17 2:57 ` Alistair Francis
2023-04-17 2:58 ` [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Alistair Francis
3 siblings, 2 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-04-11 18:35 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, richard.henderson, Daniel Henrique Barboza
This new abstract type will be used to differentiate between static and
non-static CPUs in query-cpu-definitions.
All generic CPUs were changed to be of this type. Named CPUs are kept as
TYPE_RISCV_CPU and will still be considered static.
This is the output of query-cpu-definitions after this change for the
riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false}
]}
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 2 +-
target/riscv/cpu.c | 20 ++++++++++++++++----
target/riscv/riscv-qmp-cmds.c | 4 ++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b9318e0783..b29090ad86 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -23,6 +23,7 @@
#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
+#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
@@ -66,5 +67,4 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
-
#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fab38859ec..56f2b345cf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1788,6 +1788,13 @@ void riscv_cpu_list(void)
.instance_init = initfn \
}
+#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_DYNAMIC_CPU, \
+ .instance_init = initfn \
+ }
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
},
- DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+ {
+ .name = TYPE_RISCV_DYNAMIC_CPU,
+ .parent = TYPE_RISCV_CPU,
+ .abstract = true,
+ },
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(CONFIG_KVM)
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
#endif
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 128677add9..5ecff1afb3 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
const char *typename = object_class_get_name(oc);
+ ObjectClass *dyn_class;
info->name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_RISCV_CPU));
info->q_typename = g_strdup(typename);
+ dyn_class = object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU);
+ info->q_static = dyn_class == NULL;
+
QAPI_LIST_PREPEND(*cpu_list, info);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-04-11 18:35 ` [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Daniel Henrique Barboza
@ 2023-04-12 10:18 ` Richard Henderson
2023-04-17 2:57 ` Alistair Francis
1 sibling, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2023-04-12 10:18 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu, palmer
On 4/11/23 20:35, Daniel Henrique Barboza wrote:
> This new abstract type will be used to differentiate between static and
> non-static CPUs in query-cpu-definitions.
>
> All generic CPUs were changed to be of this type. Named CPUs are kept as
> TYPE_RISCV_CPU and will still be considered static.
>
> This is the output of query-cpu-definitions after this change for the
> riscv64 target:
>
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
> {"QMP": {"version": (...)}
> {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
> {"return": {}}
> {"execute": "query-cpu-definitions"}
> {"return": [
> {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false},
> {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
> {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
> {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false},
> {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false},
> {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false}
> ]}
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu-qom.h | 2 +-
> target/riscv/cpu.c | 20 ++++++++++++++++----
> target/riscv/riscv-qmp-cmds.c | 4 ++++
> 3 files changed, 21 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-04-11 18:35 ` [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Daniel Henrique Barboza
2023-04-12 10:18 ` Richard Henderson
@ 2023-04-17 2:57 ` Alistair Francis
1 sibling, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2023-04-17 2:57 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This new abstract type will be used to differentiate between static and
> non-static CPUs in query-cpu-definitions.
>
> All generic CPUs were changed to be of this type. Named CPUs are kept as
> TYPE_RISCV_CPU and will still be considered static.
>
> This is the output of query-cpu-definitions after this change for the
> riscv64 target:
>
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
> {"QMP": {"version": (...)}
> {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
> {"return": {}}
> {"execute": "query-cpu-definitions"}
> {"return": [
> {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false},
> {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
> {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
> {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false},
> {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false},
> {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false}
> ]}
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 2 +-
> target/riscv/cpu.c | 20 ++++++++++++++++----
> target/riscv/riscv-qmp-cmds.c | 4 ++++
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index b9318e0783..b29090ad86 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -23,6 +23,7 @@
> #include "qom/object.h"
>
> #define TYPE_RISCV_CPU "riscv-cpu"
> +#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
>
> #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> @@ -66,5 +67,4 @@ struct RISCVCPUClass {
> DeviceRealize parent_realize;
> ResettablePhases parent_phases;
> };
> -
> #endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fab38859ec..56f2b345cf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1788,6 +1788,13 @@ void riscv_cpu_list(void)
> .instance_init = initfn \
> }
>
> +#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
> + { \
> + .name = type_name, \
> + .parent = TYPE_RISCV_DYNAMIC_CPU, \
> + .instance_init = initfn \
> + }
> +
> static const TypeInfo riscv_cpu_type_infos[] = {
> {
> .name = TYPE_RISCV_CPU,
> @@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .class_size = sizeof(RISCVCPUClass),
> .class_init = riscv_cpu_class_init,
> },
> - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> + {
> + .name = TYPE_RISCV_DYNAMIC_CPU,
> + .parent = TYPE_RISCV_CPU,
> + .abstract = true,
> + },
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(CONFIG_KVM)
> DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
> #endif
> #if defined(TARGET_RISCV32)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
> #elif defined(TARGET_RISCV64)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> #endif
> };
>
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> index 128677add9..5ecff1afb3 100644
> --- a/target/riscv/riscv-qmp-cmds.c
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
> CpuDefinitionInfoList **cpu_list = user_data;
> CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
> const char *typename = object_class_get_name(oc);
> + ObjectClass *dyn_class;
>
> info->name = g_strndup(typename,
> strlen(typename) - strlen("-" TYPE_RISCV_CPU));
> info->q_typename = g_strdup(typename);
>
> + dyn_class = object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU);
> + info->q_static = dyn_class == NULL;
> +
> QAPI_LIST_PREPEND(*cpu_list, info);
> }
>
> --
> 2.39.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/3] target/riscv: implement query-cpu-definitions
2023-04-11 18:35 [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Daniel Henrique Barboza
` (2 preceding siblings ...)
2023-04-11 18:35 ` [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Daniel Henrique Barboza
@ 2023-04-17 2:58 ` Alistair Francis
2023-05-03 9:51 ` Daniel Henrique Barboza
3 siblings, 1 reply; 11+ messages in thread
From: Alistair Francis @ 2023-04-17 2:58 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this v3 I removed patches 3 and 4 of v2.
>
> Patch 3 now implements a new type that the generic CPUs (any, rv32,
> rv64, x-rv128) were converted to. This type will be used by
> query-cpu-definitions to determine if a given cpu is static or not based
> on its type. This approach was suggested by Richard Henderson in the v2
> review.
>
> Patches are based on top of Alistair's riscv-to-apply.next.
>
> Changes from v2:
> - old patches 3 and 4: removed
> - patch 3:
> - add TYPE_RISCV_DYNAMIC_CPU
> - use this type to set 'q_static' in riscv_cpu_add_definition()
> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01310.html
>
> Daniel Henrique Barboza (3):
> target/riscv: add CPU QOM header
> target/riscv: add query-cpy-definitions support
> target/riscv: add TYPE_RISCV_DYNAMIC_CPU
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> qapi/machine-target.json | 6 ++-
> target/riscv/cpu-qom.h | 70 +++++++++++++++++++++++++++++++++++
> target/riscv/cpu.c | 20 ++++++++--
> target/riscv/cpu.h | 46 +----------------------
> target/riscv/meson.build | 3 +-
> target/riscv/riscv-qmp-cmds.c | 57 ++++++++++++++++++++++++++++
> 6 files changed, 150 insertions(+), 52 deletions(-)
> create mode 100644 target/riscv/cpu-qom.h
> create mode 100644 target/riscv/riscv-qmp-cmds.c
>
> --
> 2.39.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/3] target/riscv: implement query-cpu-definitions
2023-04-17 2:58 ` [PATCH v3 0/3] target/riscv: implement query-cpu-definitions Alistair Francis
@ 2023-05-03 9:51 ` Daniel Henrique Barboza
2023-05-05 1:59 ` Alistair Francis
0 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-03 9:51 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
Alistair,
Patch 2 has a typo right in the commit title:
"target/riscv: add query-cpy-definitions support"
it should be 'query-cpu-definitions'. Can you amend it in the tree? Or should
I re-send?
Thanks,
Daniel
On 4/16/23 23:58, Alistair Francis wrote:
> On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>> Hi,
>>
>> In this v3 I removed patches 3 and 4 of v2.
>>
>> Patch 3 now implements a new type that the generic CPUs (any, rv32,
>> rv64, x-rv128) were converted to. This type will be used by
>> query-cpu-definitions to determine if a given cpu is static or not based
>> on its type. This approach was suggested by Richard Henderson in the v2
>> review.
>>
>> Patches are based on top of Alistair's riscv-to-apply.next.
>>
>> Changes from v2:
>> - old patches 3 and 4: removed
>> - patch 3:
>> - add TYPE_RISCV_DYNAMIC_CPU
>> - use this type to set 'q_static' in riscv_cpu_add_definition()
>> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01310.html
>>
>> Daniel Henrique Barboza (3):
>> target/riscv: add CPU QOM header
>> target/riscv: add query-cpy-definitions support
>> target/riscv: add TYPE_RISCV_DYNAMIC_CPU
>
> Thanks!
>
> Applied to riscv-to-apply.next
>
> Alistair
>
>>
>> qapi/machine-target.json | 6 ++-
>> target/riscv/cpu-qom.h | 70 +++++++++++++++++++++++++++++++++++
>> target/riscv/cpu.c | 20 ++++++++--
>> target/riscv/cpu.h | 46 +----------------------
>> target/riscv/meson.build | 3 +-
>> target/riscv/riscv-qmp-cmds.c | 57 ++++++++++++++++++++++++++++
>> 6 files changed, 150 insertions(+), 52 deletions(-)
>> create mode 100644 target/riscv/cpu-qom.h
>> create mode 100644 target/riscv/riscv-qmp-cmds.c
>>
>> --
>> 2.39.2
>>
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/3] target/riscv: implement query-cpu-definitions
2023-05-03 9:51 ` Daniel Henrique Barboza
@ 2023-05-05 1:59 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2023-05-05 1:59 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, richard.henderson
On Wed, May 3, 2023 at 7:51 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Alistair,
>
> Patch 2 has a typo right in the commit title:
>
> "target/riscv: add query-cpy-definitions support"
>
> it should be 'query-cpu-definitions'. Can you amend it in the tree? Or should
> I re-send?
I have fixed it in my tree, so no need to resend.
I did already send the PR though. I don't think it's worth re-sending
a v2 PR for the typo
Alistair
>
>
>
> Thanks,
>
>
> Daniel
>
>
>
> On 4/16/23 23:58, Alistair Francis wrote:
> > On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
> > <dbarboza@ventanamicro.com> wrote:
> >>
> >> Hi,
> >>
> >> In this v3 I removed patches 3 and 4 of v2.
> >>
> >> Patch 3 now implements a new type that the generic CPUs (any, rv32,
> >> rv64, x-rv128) were converted to. This type will be used by
> >> query-cpu-definitions to determine if a given cpu is static or not based
> >> on its type. This approach was suggested by Richard Henderson in the v2
> >> review.
> >>
> >> Patches are based on top of Alistair's riscv-to-apply.next.
> >>
> >> Changes from v2:
> >> - old patches 3 and 4: removed
> >> - patch 3:
> >> - add TYPE_RISCV_DYNAMIC_CPU
> >> - use this type to set 'q_static' in riscv_cpu_add_definition()
> >> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01310.html
> >>
> >> Daniel Henrique Barboza (3):
> >> target/riscv: add CPU QOM header
> >> target/riscv: add query-cpy-definitions support
> >> target/riscv: add TYPE_RISCV_DYNAMIC_CPU
> >
> > Thanks!
> >
> > Applied to riscv-to-apply.next
> >
> > Alistair
> >
> >>
> >> qapi/machine-target.json | 6 ++-
> >> target/riscv/cpu-qom.h | 70 +++++++++++++++++++++++++++++++++++
> >> target/riscv/cpu.c | 20 ++++++++--
> >> target/riscv/cpu.h | 46 +----------------------
> >> target/riscv/meson.build | 3 +-
> >> target/riscv/riscv-qmp-cmds.c | 57 ++++++++++++++++++++++++++++
> >> 6 files changed, 150 insertions(+), 52 deletions(-)
> >> create mode 100644 target/riscv/cpu-qom.h
> >> create mode 100644 target/riscv/riscv-qmp-cmds.c
> >>
> >> --
> >> 2.39.2
> >>
> >>
^ permalink raw reply [flat|nested] 11+ messages in thread