* [PULL 00/89] riscv-to-apply queue
@ 2023-05-05 1:01 Alistair Francis
2023-05-05 1:01 ` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Alistair Francis
` (90 more replies)
0 siblings, 91 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
----------------------------------------------------------------
First RISC-V PR for 8.1
* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU
----------------------------------------------------------------
Alexandre Ghiti (1):
riscv: Make sure an exception is raised if a pte is malformed
Bin Meng (1):
target/riscv: Restore the predicate() NULL check behavior
Conor Dooley (1):
target/riscv: fix invalid riscv,event-to-mhpmcounters entry
Daniel Henrique Barboza (23):
target/riscv: sync env->misa_ext* with cpu->cfg in realize()
target/riscv: remove MISA properties from isa_edata_arr[]
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
target/riscv: introduce riscv_cpu_add_misa_properties()
target/riscv: remove cpu->cfg.ext_a
target/riscv: remove cpu->cfg.ext_c
target/riscv: remove cpu->cfg.ext_d
target/riscv: remove cpu->cfg.ext_f
target/riscv: remove cpu->cfg.ext_i
target/riscv: remove cpu->cfg.ext_e
target/riscv: remove cpu->cfg.ext_m
target/riscv: remove cpu->cfg.ext_s
target/riscv: remove cpu->cfg.ext_u
target/riscv: remove cpu->cfg.ext_h
target/riscv: remove cpu->cfg.ext_j
target/riscv: remove cpu->cfg.ext_v
target/riscv: remove riscv_cpu_sync_misa_cfg()
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
target/riscv: add RVG and remove cpu->cfg.ext_g
target/riscv/cpu.c: redesign register_cpu_props()
target/riscv: add CPU QOM header
target/riscv: add query-cpy-definitions support
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
Fei Wu (2):
target/riscv: Separate priv from mmu_idx
target/riscv: Reduce overhead of MSTATUS_SUM change
Irina Ryapolova (1):
target/riscv: Fix Guest Physical Address Translation
Ivan Klokov (1):
hw/intc/riscv_aplic: Zero init APLIC internal state
LIU Zhiwei (7):
target/riscv: Fix priv version dependency for vector and zfh
target/riscv: Fix itrigger when icount is used
target/riscv: Convert env->virt to a bool env->virt_enabled
target/riscv: Extract virt enabled state from tb flags
target/riscv: Add a general status enum for extensions
target/riscv: Encode the FS and VS on a normal way for tb flags
target/riscv: Add a tb flags field for vstart
Philipp Tomsich (2):
target/riscv: refactor Zicond support
target/riscv: redirect XVentanaCondOps to use the Zicond functions
Rahul Pathak (1):
target/riscv: add Ventana's Veyron V1 CPU
Richard Henderson (18):
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
target/riscv: Use cpu_ld*_code_mmu for HLVX
target/riscv: Handle HLV, HSV via helpers
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
target/riscv: Introduce mmuidx_sum
target/riscv: Introduce mmuidx_priv
target/riscv: Introduce mmuidx_2stage
target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: Check SUM in the correct register
target/riscv: Hoist second stage mode change to callers
target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: Move leaf pte processing out of level loop
target/riscv: Suppress pte update with is_debug
target/riscv: Don't modify SUM with is_debug
target/riscv: Merge checks for reserved pte flags
target/riscv: Reorg access check in get_physical_address
target/riscv: Reorg sum check in get_physical_address
Weiwei Li (30):
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
target/riscv: Simplify getting RISCVCPU pointer from env
target/riscv: Simplify type conversion for CPURISCVState
target/riscv: Simplify arguments for riscv_csrrw_check
target/riscv: add cfg properties for Zc* extension
target/riscv: add support for Zca extension
target/riscv: add support for Zcf extension
target/riscv: add support for Zcd extension
target/riscv: add support for Zcb extension
target/riscv: add support for Zcmp extension
target/riscv: add support for Zcmt extension
target/riscv: expose properties for Zc* extension
disas/riscv.c: add disasm support for Zc*
target/riscv: Add support for Zce
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
target/riscv: Remove redundant check on RVH
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
target/riscv: Remove redundant parentheses
target/riscv: Fix addr type for get_physical_address
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
target/riscv: Remove riscv_cpu_virt_enabled()
target/riscv: Fix format for indentation
target/riscv: Fix format for comments
target/riscv: Fix lines with over 80 characters
hw/riscv: Add signature dump function for spike to run ACT tests
target/riscv: Fix the mstatus.MPP value after executing MRET
target/riscv: Use PRV_RESERVED instead of PRV_H
target/riscv: Legalize MPP value in write_mstatus
target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
Yi Chen (1):
target/riscv: fix H extension TVM trap
MAINTAINERS | 2 +-
qapi/machine-target.json | 6 +-
include/hw/char/riscv_htif.h | 3 +
target/riscv/cpu-qom.h | 71 +++
target/riscv/cpu.h | 155 ++---
target/riscv/cpu_bits.h | 27 +-
target/riscv/cpu_vendorid.h | 4 +
target/riscv/helper.h | 15 +-
target/riscv/internals.h | 35 ++
target/riscv/pmp.h | 9 +-
target/riscv/sbi_ecall_interface.h | 8 +-
target/riscv/time_helper.h | 2 +-
target/riscv/insn16.decode | 62 +-
disas/riscv.c | 228 ++++++-
hw/char/riscv_htif.c | 44 +-
hw/intc/riscv_aplic.c | 2 +-
hw/riscv/spike.c | 13 +
target/riscv/arch_dump.c | 7 +-
target/riscv/cpu.c | 571 +++++++++++-------
target/riscv/cpu_helper.c | 671 +++++++++++----------
target/riscv/csr.c | 331 +++++-----
target/riscv/debug.c | 21 +-
target/riscv/fpu_helper.c | 24 +-
target/riscv/gdbstub.c | 9 +-
target/riscv/m128_helper.c | 16 +-
target/riscv/machine.c | 43 +-
target/riscv/op_helper.c | 147 ++++-
target/riscv/pmp.c | 66 +-
target/riscv/pmu.c | 23 +-
target/riscv/riscv-qmp-cmds.c | 57 ++
target/riscv/time_helper.c | 15 +-
target/riscv/translate.c | 109 ++--
target/riscv/vector_helper.c | 317 +++++-----
target/riscv/zce_helper.c | 55 ++
target/riscv/insn_trans/trans_privileged.c.inc | 8 +-
target/riscv/insn_trans/trans_rvd.c.inc | 18 +
target/riscv/insn_trans/trans_rvf.c.inc | 20 +-
target/riscv/insn_trans/trans_rvh.c.inc | 127 ++--
target/riscv/insn_trans/trans_rvi.c.inc | 4 +-
target/riscv/insn_trans/trans_rvv.c.inc | 58 +-
target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++
target/riscv/insn_trans/trans_rvzicond.c.inc | 36 +-
target/riscv/insn_trans/trans_xthead.c.inc | 14 +-
.../riscv/insn_trans/trans_xventanacondops.c.inc | 18 +-
target/riscv/meson.build | 6 +-
45 files changed, 2488 insertions(+), 1300 deletions(-)
create mode 100644 target/riscv/cpu-qom.h
create mode 100644 target/riscv/riscv-qmp-cmds.c
create mode 100644 target/riscv/zce_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
^ permalink raw reply [flat|nested] 97+ messages in thread
* [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Alistair Francis
` (89 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 9 ++++-----
target/riscv/csr.c | 40 ++++++++++++---------------------------
target/riscv/gdbstub.c | 4 ++--
3 files changed, 18 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..e677255f87 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, uint8_t *iprio)
{
- RISCVCPU *cpu = env_archcpu(env);
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
@@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
}
irq = ctz64(pending);
- if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
+ if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
+ riscv_cpu_cfg(env)->ext_ssaia)) {
return irq;
}
@@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
hwaddr ppn;
- RISCVCPU *cpu = env_archcpu(env);
int napot_bits = 0;
target_ulong napot_mask;
@@ -946,7 +945,7 @@ restart:
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
- } else if (pbmte || cpu->cfg.ext_svnapot) {
+ } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
ppn = pte >> PTE_PPN_SHIFT;
@@ -1043,7 +1042,7 @@ restart:
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
napot_bits = ctzl(ppn) + 1;
if ((i != (levels - 1)) || (napot_bits != 4)) {
return TRANSLATE_FAIL;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..70468572fe 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -89,9 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (cpu->cfg.ext_zve32f) {
+ if (riscv_cpu_cfg(env)->ext_zve32f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -194,9 +192,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_sscofpmf) {
+ if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -311,9 +307,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -322,9 +316,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -391,10 +383,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
static RISCVException sstc(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
bool hmode_check = false;
- if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+ if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -1171,27 +1162,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.mvendorid;
+ *val = riscv_cpu_cfg(env)->mvendorid;
return RISCV_EXCP_NONE;
}
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.marchid;
+ *val = riscv_cpu_cfg(env)->marchid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.mimpid;
+ *val = riscv_cpu_cfg(env)->mimpid;
return RISCV_EXCP_NONE;
}
@@ -1233,9 +1218,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
-
- return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+ return (vm & 0xf) <=
+ satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
}
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
@@ -1898,7 +1882,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -1921,7 +1905,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0);
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 840d1ec5c6..692bbb64f6 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
- uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
{
- uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:01 ` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Alistair Francis
` (88 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..eaf75a00a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -84,7 +84,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
- ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
+ ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
@@ -104,9 +104,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
- ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
- ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
- ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
+ ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f),
+ ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f),
+ ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d),
ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:01 ` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Alistair Francis
2023-05-05 1:01 ` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Alistair Francis
` (87 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Daniel Henrique Barboza, Philippe Mathieu-Daudé
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx)
{
uint32_t event_idx;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
return -1;
@@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
{
uint64_t overflow_delta, overflow_at;
int64_t overflow_ns, overflow_left = 0;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2023-05-05 1:01 ` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check Alistair Francis
` (86 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 ++-
target/riscv/time_helper.h | 2 +-
target/riscv/cpu.c | 6 +++---
target/riscv/cpu_helper.c | 8 ++++----
target/riscv/csr.c | 35 +++++++++++------------------------
target/riscv/pmu.c | 6 +++---
target/riscv/time_helper.c | 15 +++++++--------
7 files changed, 31 insertions(+), 44 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..5adefe4ab5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
+ uint64_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
void *arg);
diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
index 7b3cdcc350..cacd79b80c 100644
--- a/target/riscv/time_helper.h
+++ b/target/riscv/time_helper.h
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "qemu/timer.h"
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint64_t timecmp, uint64_t delta,
uint32_t timer_irq);
void riscv_timer_init(RISCVCPU *cpu);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eaf75a00a6..cea0d3cbdd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
} else {
- riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+ riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
}
break;
case IRQ_S_EXT:
@@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
kvm_riscv_set_irq(cpu, irq, level);
} else {
env->external_seip = level;
- riscv_cpu_update_mip(cpu, 1 << irq,
+ riscv_cpu_update_mip(env, 1 << irq,
BOOL_TO_MASK(level | env->software_seip));
}
break;
@@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
}
/* Update mip.SGEIP bit */
- riscv_cpu_update_mip(cpu, MIP_SGEIP,
+ riscv_cpu_update_mip(env, MIP_SGEIP,
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
} else {
g_assert_not_reached();
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e677255f87..824f0cbd92 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
*
* To solve this, we check and inject interrupt after setting V=1.
*/
- riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ riscv_cpu_update_mip(env, 0, 0);
}
}
@@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
}
}
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
+ uint64_t value)
{
- CPURISCVState *env = &cpu->env;
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
if (riscv_cpu_virt_enabled(env)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 70468572fe..a7d0157d33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -991,15 +991,13 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (riscv_cpu_mxl(env) == MXL_RV32) {
env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
} else {
env->vstimecmp = val;
}
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
@@ -1008,10 +1006,8 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
@@ -1044,8 +1040,6 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -1059,7 +1053,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
env->stimecmp = val;
}
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
@@ -1067,8 +1061,6 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -1077,7 +1069,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
}
env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
@@ -2212,7 +2204,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
{
- RISCVCPU *cpu = env_archcpu(env);
uint64_t old_mip, mask = wr_mask & delegable_ints;
uint32_t gin;
@@ -2221,14 +2212,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
new_val |= env->external_seip * MIP_SEIP;
}
- if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
+ if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
get_field(env->menvcfg, MENVCFG_STCE)) {
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
mask = mask & ~(MIP_STIP | MIP_VSTIP);
}
if (mask) {
- old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
+ old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
} else {
old_mip = env->mip;
}
@@ -2988,7 +2979,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
env->hgeie = val;
/* Update mip.SGEIP bit */
- riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+ riscv_cpu_update_mip(env, MIP_SGEIP,
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
return RISCV_EXCP_NONE;
}
@@ -3057,8 +3048,6 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3069,8 +3058,8 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
env->htimedelta = val;
}
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
@@ -3091,16 +3080,14 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a200741083..22e2283c76 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
/* Generate interrupt only if OF bit is clear */
if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
} else {
counter->mhpmcounterh_val++;
@@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
/* Generate interrupt only if OF bit is clear */
if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
} else {
counter->mhpmcounter_val++;
@@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
/* Generate interrupt only if OF bit is clear */
if (!(*mhpmevent_val & of_bit_mask)) {
*mhpmevent_val |= of_bit_mask;
- riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
}
}
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index b654f91af9..8d245bed3a 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque)
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
- riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
}
/*
* Called when timecmp is written to update the QEMU timer or immediately
* trigger timer interrupt if mtimecmp <= current timer value.
*/
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint64_t timecmp, uint64_t delta,
uint32_t timer_irq)
{
uint64_t diff, ns_diff, next;
- CPURISCVState *env = &cpu->env;
RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
uint32_t timebase_freq = mtimer->timebase_freq;
uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
@@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
} else {
- riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
}
return;
}
@@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
/* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
- riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
+ riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
} else {
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
+ riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
}
/*
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2023-05-05 1:01 ` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 06/89] target/riscv: refactor Zicond support Alistair Francis
` (85 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Daniel Henrique Barboza, Philippe Mathieu-Daudé
From: Weiwei Li <liweiwei@iscas.ac.cn>
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a7d0157d33..8f4d5eb13f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3756,15 +3756,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno,
- bool write_mask,
- RISCVCPU *cpu)
+ bool write_mask)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */
- if (!cpu->cfg.ext_icsr) {
+ if (!riscv_cpu_cfg(env)->ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3860,9 +3859,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+ RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
@@ -3915,9 +3912,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 new_value, Int128 write_mask)
{
RISCVException ret;
- RISCVCPU *cpu = env_archcpu(env);
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
+ ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
if (ret != RISCV_EXCP_NONE) {
return ret;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 06/89] target/riscv: refactor Zicond support
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2023-05-05 1:01 ` [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Alistair Francis
` (84 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philipp Tomsich, Richard Henderson, Alistair Francis
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
After the original Zicond support was stuck/fell through the cracks on
the mailing list at v3 (and a different implementation was merged in
the meanwhile), we need to refactor Zicond to prepare it to be reused
by XVentanaCondOps.
This commit lifts the common logic out into gen_czero and uses this
via gen_logic and 2 helper functions (effectively partial closures).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvzicond.c.inc | 36 ++++++++++++--------
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/insn_trans/trans_rvzicond.c.inc
index 645260164e..c8e43fa325 100644
--- a/target/riscv/insn_trans/trans_rvzicond.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicond.c.inc
@@ -2,6 +2,7 @@
* RISC-V translation routines for the Zicond Standard Extension.
*
* Copyright (c) 2020-2023 PLCT Lab
+ * Copyright (c) 2022 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -22,28 +23,33 @@
} \
} while (0)
-static bool trans_czero_eqz(DisasContext *ctx, arg_czero_eqz *a)
+/* Emits "$rd = ($rs2 <cond> $zero) ? $zero : $rs1" */
+static void gen_czero(TCGv dest, TCGv src1, TCGv src2, TCGCond cond)
{
- REQUIRE_ZICOND(ctx);
+ TCGv zero = tcg_constant_tl(0);
+ tcg_gen_movcond_tl(cond, dest, src2, zero, zero, src1);
+}
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+static void gen_czero_eqz(TCGv dest, TCGv src1, TCGv src2)
+{
+ gen_czero(dest, src1, src2, TCG_COND_EQ);
+}
- tcg_gen_movcond_tl(TCG_COND_EQ, dest, src2, ctx->zero, ctx->zero, src1);
- gen_set_gpr(ctx, a->rd, dest);
- return true;
+static void gen_czero_nez(TCGv dest, TCGv src1, TCGv src2)
+{
+ gen_czero(dest, src1, src2, TCG_COND_NE);
}
-static bool trans_czero_nez(DisasContext *ctx, arg_czero_nez *a)
+static bool trans_czero_eqz(DisasContext *ctx, arg_r *a)
{
REQUIRE_ZICOND(ctx);
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ return gen_logic(ctx, a, gen_czero_eqz);
+}
+
+static bool trans_czero_nez(DisasContext *ctx, arg_r *a)
+{
+ REQUIRE_ZICOND(ctx);
- tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, ctx->zero, ctx->zero, src1);
- gen_set_gpr(ctx, a->rd, dest);
- return true;
+ return gen_logic(ctx, a, gen_czero_nez);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2023-05-05 1:01 ` [PULL 06/89] target/riscv: refactor Zicond support Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Alistair Francis
` (83 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philipp Tomsich, Richard Henderson, Alistair Francis
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.
Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.
Also updating MAINTAINERS as trans_xventanacondops.c.inc.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 2 +-
.../insn_trans/trans_xventanacondops.c.inc | 18 +++---------------
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b22b85bc3a..431556c217 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -328,7 +328,7 @@ F: target/riscv/xthead*.decode
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
L: qemu-riscv@nongnu.org
-S: Supported
+S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
index 16849e6d4e..38c15f2825 100644
--- a/target/riscv/insn_trans/trans_xventanacondops.c.inc
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -1,7 +1,7 @@
/*
* RISC-V translation routines for the XVentanaCondOps extension.
*
- * Copyright (c) 2021-2022 VRULL GmbH.
+ * Copyright (c) 2021-2023 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -16,24 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
- tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
-
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
-
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
{
- return gen_vt_condmask(ctx, a, TCG_COND_NE);
+ return gen_logic(ctx, a, gen_czero_eqz);
}
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
{
- return gen_vt_condmask(ctx, a, TCG_COND_EQ);
+ return gen_logic(ctx, a, gen_czero_nez);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2023-05-05 1:01 ` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 09/89] target/riscv: add cfg properties for Zc* extension Alistair Francis
` (82 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Conor Dooley, Alistair Francis
From: Conor Dooley <conor.dooley@microchip.com>
dt-validate complains:
> soc: pmu: {'riscv,event-to-mhpmcounters':
> [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280],
> [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]],
> pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short
There are bogus 0 entries added at the end, of which one is of
insufficient length. This happens because only 15 of
fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is
called using the size of the array.
Reduce the array to 15 elements to make the error go away.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230404173333.35179-1-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 22e2283c76..96ce2dbe49 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -35,7 +35,7 @@
*/
void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
{
- uint32_t fdt_event_ctr_map[20] = {};
+ uint32_t fdt_event_ctr_map[15] = {};
uint32_t cmask;
/* All the programmable counters can map to any event */
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 09/89] target/riscv: add cfg properties for Zc* extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2023-05-05 1:01 ` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 10/89] target/riscv: add support for Zca extension Alistair Francis
` (81 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension.
Add check for these properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 ++++++
target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5adefe4ab5..e5f7c860d1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -438,6 +438,12 @@ struct RISCVCPUConfig {
bool ext_zbkc;
bool ext_zbkx;
bool ext_zbs;
+ bool ext_zca;
+ bool ext_zcb;
+ bool ext_zcd;
+ bool ext_zcf;
+ bool ext_zcmp;
+ bool ext_zcmt;
bool ext_zk;
bool ext_zkn;
bool ext_zknd;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cea0d3cbdd..97b0a77d8e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -939,6 +939,49 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
+ if (cpu->cfg.ext_c) {
+ cpu->cfg.ext_zca = true;
+ if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
+ cpu->cfg.ext_zcf = true;
+ }
+ if (cpu->cfg.ext_d) {
+ cpu->cfg.ext_zcd = true;
+ }
+ }
+
+ if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension is only relevant to RV32");
+ return;
+ }
+
+ if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension requires F extension");
+ return;
+ }
+
+ if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
+ error_setg(errp, "Zcd extension requires D extension");
+ return;
+ }
+
+ if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+ cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+ error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
+ "extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+ error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
+ "Zcd extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+ error_setg(errp, "Zcmt extension requires Zicsr extension");
+ return;
+ }
+
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 10/89] target/riscv: add support for Zca extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2023-05-05 1:01 ` [PULL 09/89] target/riscv: add cfg properties for Zc* extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 11/89] target/riscv: add support for Zcf extension Alistair Francis
` (80 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis, Wilfred Mallawa
From: Weiwei Li <liweiwei@iscas.ac.cn>
Modify the check for C extension to Zca (C implies Zca).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 8 ++++++--
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0ee8ee147d..d1fdd0c2d7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -549,7 +549,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -1122,7 +1122,11 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
if (insn_len(opcode) == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
+ /*
+ * The Zca extension is added as way to refer to instructions in the C
+ * extension that do not include the floating-point loads and stores
+ */
+ if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
return;
}
} else {
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 4ad54e8a49..c70c495fc5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
gen_set_pc(ctx, cpu_pc);
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@@ -169,7 +169,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 11/89] target/riscv: add support for Zcf extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2023-05-05 1:01 ` [PULL 10/89] target/riscv: add support for Zca extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 12/89] target/riscv: add support for Zcd extension Alistair Francis
` (79 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 8 ++++----
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index ccfe59f294..f3ea650325 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
{
ld 011 ... ... .. ... 00 @cl_d
- flw 011 ... ... .. ... 00 @cl_w
+ c_flw 011 ... ... .. ... 00 @cl_w
}
{
sd 111 ... ... .. ... 00 @cs_d
- fsw 111 ... ... .. ... 00 @cs_w
+ c_fsw 111 ... ... .. ... 00 @cs_w
}
# *** RV32/64C Standard Extension (Quadrant 1) ***
@@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp
{
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
ld 011 . ..... ..... 10 @c_ldsp
- flw 011 . ..... ..... 10 @c_lwsp
+ c_flw 011 . ..... ..... 10 @c_lwsp
}
{
sd 111 . ..... ..... 10 @c_sdsp
- fsw 111 . ..... ..... 10 @c_swsp
+ c_fsw 111 . ..... ..... 10 @c_swsp
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 052408f45c..9e9fa2087a 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,12 @@
} \
} while (0)
+#define REQUIRE_ZCF(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcf) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv_i64 dest;
@@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
return true;
}
+static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
+{
+ REQUIRE_ZCF(ctx);
+ return trans_flw(ctx, a);
+}
+
+static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ REQUIRE_ZCF(ctx);
+ return trans_fsw(ctx, a);
+}
+
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
{
REQUIRE_FPU;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 12/89] target/riscv: add support for Zcd extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2023-05-05 1:01 ` [PULL 11/89] target/riscv: add support for Zcf extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 13/89] target/riscv: add support for Zcb extension Alistair Francis
` (78 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 8 ++++----
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index f3ea650325..b62664b6af 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -97,12 +97,12 @@
}
{
lq 001 ... ... .. ... 00 @cl_q
- fld 001 ... ... .. ... 00 @cl_d
+ c_fld 001 ... ... .. ... 00 @cl_d
}
lw 010 ... ... .. ... 00 @cl_w
{
sq 101 ... ... .. ... 00 @cs_q
- fsd 101 ... ... .. ... 00 @cs_d
+ c_fsd 101 ... ... .. ... 00 @cs_d
}
sw 110 ... ... .. ... 00 @cs_w
@@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2
slli 000 . ..... ..... 10 @c_shift2
{
lq 001 ... ... .. ... 10 @c_lqsp
- fld 001 . ..... ..... 10 @c_ldsp
+ c_fld 001 . ..... ..... 10 @c_ldsp
}
{
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
@@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2
}
{
sq 101 ... ... .. ... 10 @c_sqsp
- fsd 101 ...... ..... 10 @c_sdsp
+ c_fsd 101 ...... ..... 10 @c_sdsp
}
sw 110 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 1597bf31d8..2c51e01c40 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -31,6 +31,12 @@
} \
} while (0)
+#define REQUIRE_ZCD(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcd) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
TCGv addr;
@@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
return true;
}
+static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
+{
+ REQUIRE_ZCD(ctx);
+ return trans_fld(ctx, a);
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ REQUIRE_ZCD(ctx);
+ return trans_fsd(ctx, a);
+}
+
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
{
REQUIRE_FPU;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 13/89] target/riscv: add support for Zcb extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2023-05-05 1:01 ` [PULL 12/89] target/riscv: add support for Zcd extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 14/89] target/riscv: add support for Zcmp extension Alistair Francis
` (77 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add encode and trans* functions support for Zcb instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 23 +++++
target/riscv/translate.c | 2 +
target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b62664b6af..ab780fa46a 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -43,6 +43,8 @@
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
+%uimm_cl_b 5:1 6:1
+%uimm_cl_h 5:1 !function=ex_shift_1
# Argument sets imported from insn32.decode:
&empty !extern
@@ -53,6 +55,7 @@
&b imm rs2 rs1 !extern
&u imm rd !extern
&shift shamt rs1 rd !extern
+&r2 rd rs1 !extern
# Formats 16:
@@ -89,6 +92,12 @@
@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
+@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
+@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
+@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
+@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
+@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
+
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
@@ -180,3 +189,17 @@ sw 110 . ..... ..... 10 @c_swsp
sd 111 . ..... ..... 10 @c_sdsp
c_fsw 111 . ..... ..... 10 @c_swsp
}
+
+# *** RV64 and RV32 Zcb Extension ***
+c_zext_b 100 111 ... 11 000 01 @cu
+c_sext_b 100 111 ... 11 001 01 @cu
+c_zext_h 100 111 ... 11 010 01 @cu
+c_sext_h 100 111 ... 11 011 01 @cu
+c_zext_w 100 111 ... 11 100 01 @cu
+c_not 100 111 ... 11 101 01 @cu
+c_mul 100 111 ... 10 ... 01 @cs_2
+c_lbu 100 000 ... .. ... 00 @cl_b
+c_lhu 100 001 ... 0. ... 00 @cl_h
+c_lh 100 001 ... 1. ... 00 @cl_h
+c_sb 100 010 ... .. ... 00 @cs_b
+c_sh 100 011 ... 0. ... 00 @cs_h
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d1fdd0c2d7..3634137d85 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1091,6 +1091,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
+#include "insn_trans/trans_rvzce.c.inc"
+
/* Include decoders for factored-out extensions */
#include "decode-XVentanaCondOps.c.inc"
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
new file mode 100644
index 0000000000..de96c4afaf
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -0,0 +1,100 @@
+/*
+ * RISC-V translation routines for the Zcb Standard Extension.
+ *
+ * Copyright (c) 2021-2022 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZCB(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcb) \
+ return false; \
+} while (0)
+
+static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl);
+}
+
+static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a)
+{
+ REQUIRE_ZCB(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
+}
+
+static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a)
+{
+ REQUIRE_ZCB(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
+}
+
+static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a)
+{
+ REQUIRE_ZCB(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
+}
+
+static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZCB(ctx);
+ REQUIRE_ZBA(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl);
+}
+
+static bool trans_c_not(DisasContext *ctx, arg_c_not *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl);
+}
+
+static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a)
+{
+ REQUIRE_ZCB(ctx);
+ REQUIRE_M_OR_ZMMUL(ctx);
+ return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
+}
+
+static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_load(ctx, a, MO_UB);
+}
+
+static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_load(ctx, a, MO_UW);
+}
+
+static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_load(ctx, a, MO_SW);
+}
+
+static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_store(ctx, a, MO_UB);
+}
+
+static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
+{
+ REQUIRE_ZCB(ctx);
+ return gen_store(ctx, a, MO_UW);
+}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 14/89] target/riscv: add support for Zcmp extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2023-05-05 1:01 ` [PULL 13/89] target/riscv: add support for Zcb extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 15/89] target/riscv: add support for Zcmt extension Alistair Francis
` (76 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add encode, trans* functions for Zcmp instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 18 +++
target/riscv/translate.c | 5 +
target/riscv/insn_trans/trans_rvzce.c.inc | 187 +++++++++++++++++++++-
3 files changed, 209 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index ab780fa46a..55c9574299 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -21,6 +21,8 @@
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
%rs2_5 2:5
+%r1s 7:3 !function=ex_sreg_register
+%r2s 2:3 !function=ex_sreg_register
# Immediates:
%imm_ci 12:s1 2:5
@@ -45,6 +47,8 @@
%uimm_cl_b 5:1 6:1
%uimm_cl_h 5:1 !function=ex_shift_1
+%spimm 2:2 !function=ex_shift_4
+%urlist 4:4
# Argument sets imported from insn32.decode:
&empty !extern
@@ -56,7 +60,9 @@
&u imm rd !extern
&shift shamt rs1 rd !extern
&r2 rd rs1 !extern
+&r2_s rs1 rs2 !extern
+&cmpp urlist spimm
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@@ -97,6 +103,8 @@
@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
+@cm_pp ... ... ........ .. &cmpp %urlist %spimm
+@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
@@ -176,6 +184,16 @@ slli 000 . ..... ..... 10 @c_shift2
{
sq 101 ... ... .. ... 10 @c_sqsp
c_fsd 101 ...... ..... 10 @c_sdsp
+
+ # *** RV64 and RV32 Zcmp Extension ***
+ [
+ cm_push 101 11000 .... .. 10 @cm_pp
+ cm_pop 101 11010 .... .. 10 @cm_pp
+ cm_popret 101 11110 .... .. 10 @cm_pp
+ cm_popretz 101 11100 .... .. 10 @cm_pp
+ cm_mva01s 101 011 ... 11 ... 10 @cm_mv
+ cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
+ ]
}
sw 110 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3634137d85..6872d17fb9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -757,6 +757,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg)
return 8 + reg;
}
+static int ex_sreg_register(DisasContext *ctx, int reg)
+{
+ return reg < 2 ? reg + 8 : reg + 16;
+}
+
static int ex_rvc_shiftli(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index de96c4afaf..a47959eb67 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zcb Standard Extension.
+ * RISC-V translation routines for the Zc[b,mp] Standard Extensions.
*
* Copyright (c) 2021-2022 PLCT Lab
*
@@ -21,6 +21,11 @@
return false; \
} while (0)
+#define REQUIRE_ZCMP(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcmp) \
+ return false; \
+} while (0)
+
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
{
REQUIRE_ZCB(ctx);
@@ -98,3 +103,183 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_UW);
}
+
+#define X_S0 8
+#define X_S1 9
+#define X_Sn 16
+
+static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
+{
+ uint32_t reg_bitmap = 0;
+
+ if (ctx->cfg_ptr->ext_e && rlist > 6) {
+ return 0;
+ }
+
+ switch (rlist) {
+ case 15:
+ reg_bitmap |= 1 << (X_Sn + 11) ;
+ reg_bitmap |= 1 << (X_Sn + 10) ;
+ /* FALL THROUGH */
+ case 14:
+ reg_bitmap |= 1 << (X_Sn + 9) ;
+ /* FALL THROUGH */
+ case 13:
+ reg_bitmap |= 1 << (X_Sn + 8) ;
+ /* FALL THROUGH */
+ case 12:
+ reg_bitmap |= 1 << (X_Sn + 7) ;
+ /* FALL THROUGH */
+ case 11:
+ reg_bitmap |= 1 << (X_Sn + 6) ;
+ /* FALL THROUGH */
+ case 10:
+ reg_bitmap |= 1 << (X_Sn + 5) ;
+ /* FALL THROUGH */
+ case 9:
+ reg_bitmap |= 1 << (X_Sn + 4) ;
+ /* FALL THROUGH */
+ case 8:
+ reg_bitmap |= 1 << (X_Sn + 3) ;
+ /* FALL THROUGH */
+ case 7:
+ reg_bitmap |= 1 << (X_Sn + 2) ;
+ /* FALL THROUGH */
+ case 6:
+ reg_bitmap |= 1 << X_S1 ;
+ /* FALL THROUGH */
+ case 5:
+ reg_bitmap |= 1 << X_S0;
+ /* FALL THROUGH */
+ case 4:
+ reg_bitmap |= 1 << xRA;
+ break;
+ default:
+ break;
+ }
+
+ return reg_bitmap;
+}
+
+static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
+{
+ REQUIRE_ZCMP(ctx);
+
+ uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist);
+ if (reg_bitmap == 0) {
+ return false;
+ }
+
+ MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
+ int reg_size = memop_size(memop);
+ target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) +
+ a->spimm;
+ TCGv sp = dest_gpr(ctx, xSP);
+ TCGv addr = tcg_temp_new();
+ int i;
+
+ tcg_gen_addi_tl(addr, sp, stack_adj - reg_size);
+
+ for (i = X_Sn + 11; i >= 0; i--) {
+ if (reg_bitmap & (1 << i)) {
+ TCGv dest = dest_gpr(ctx, i);
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, i, dest);
+ tcg_gen_subi_tl(addr, addr, reg_size);
+ }
+ }
+
+ tcg_gen_addi_tl(sp, sp, stack_adj);
+ gen_set_gpr(ctx, xSP, sp);
+
+ if (ret_val) {
+ gen_set_gpr(ctx, xA0, ctx->zero);
+ }
+
+ if (ret) {
+ TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE);
+ gen_set_pc(ctx, ret_addr);
+ tcg_gen_lookup_and_goto_ptr();
+ ctx->base.is_jmp = DISAS_NORETURN;
+ }
+
+ return true;
+}
+
+static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a)
+{
+ REQUIRE_ZCMP(ctx);
+
+ uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist);
+ if (reg_bitmap == 0) {
+ return false;
+ }
+
+ MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
+ int reg_size = memop_size(memop);
+ target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) +
+ a->spimm;
+ TCGv sp = dest_gpr(ctx, xSP);
+ TCGv addr = tcg_temp_new();
+ int i;
+
+ tcg_gen_subi_tl(addr, sp, reg_size);
+
+ for (i = X_Sn + 11; i >= 0; i--) {
+ if (reg_bitmap & (1 << i)) {
+ TCGv val = get_gpr(ctx, i, EXT_NONE);
+ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, memop);
+ tcg_gen_subi_tl(addr, addr, reg_size);
+ }
+ }
+
+ tcg_gen_subi_tl(sp, sp, stack_adj);
+ gen_set_gpr(ctx, xSP, sp);
+
+ return true;
+}
+
+static bool trans_cm_pop(DisasContext *ctx, arg_cm_pop *a)
+{
+ return gen_pop(ctx, a, false, false);
+}
+
+static bool trans_cm_popret(DisasContext *ctx, arg_cm_popret *a)
+{
+ return gen_pop(ctx, a, true, false);
+}
+
+static bool trans_cm_popretz(DisasContext *ctx, arg_cm_popret *a)
+{
+ return gen_pop(ctx, a, true, true);
+}
+
+static bool trans_cm_mva01s(DisasContext *ctx, arg_cm_mva01s *a)
+{
+ REQUIRE_ZCMP(ctx);
+
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_set_gpr(ctx, xA0, src1);
+ gen_set_gpr(ctx, xA1, src2);
+
+ return true;
+}
+
+static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a)
+{
+ REQUIRE_ZCMP(ctx);
+
+ if (a->rs1 == a->rs2) {
+ return false;
+ }
+
+ TCGv a0 = get_gpr(ctx, xA0, EXT_NONE);
+ TCGv a1 = get_gpr(ctx, xA1, EXT_NONE);
+
+ gen_set_gpr(ctx, a->rs1, a0);
+ gen_set_gpr(ctx, a->rs2, a1);
+
+ return true;
+}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 15/89] target/riscv: add support for Zcmt extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2023-05-05 1:01 ` [PULL 14/89] target/riscv: add support for Zcmp extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 16/89] target/riscv: expose properties for Zc* extension Alistair Francis
` (75 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 7 +++
target/riscv/helper.h | 3 ++
target/riscv/insn16.decode | 7 ++-
target/riscv/csr.c | 36 ++++++++++++++-
target/riscv/machine.c | 19 ++++++++
target/riscv/zce_helper.c | 55 +++++++++++++++++++++++
target/riscv/insn_trans/trans_rvzce.c.inc | 28 +++++++++++-
target/riscv/meson.build | 3 +-
9 files changed, 157 insertions(+), 5 deletions(-)
create mode 100644 target/riscv/zce_helper.c
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e5f7c860d1..8d66365f60 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -176,6 +176,8 @@ struct CPUArchState {
/* 128-bit helpers upper part return value */
target_ulong retxh;
+ target_ulong jvt;
+
#ifdef CONFIG_USER_ONLY
uint32_t elf_flags;
#endif
@@ -620,6 +622,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
target_ulong new_val,
target_ulong write_mask),
void *rmw_fn_arg);
+
+RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fca7ef0cef..a92313a06f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -319,6 +319,7 @@
#define SMSTATEEN_MAX_COUNT 4
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
+#define SMSTATEEN0_JVT (1ULL << 2)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)
@@ -523,6 +524,9 @@
/* Crypto Extension */
#define CSR_SEED 0x015
+/* Zcmt Extension */
+#define CSR_JVT 0x017
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -898,4 +902,7 @@ typedef enum RISCVException {
#define MHPMEVENT_IDX_MASK 0xFFFFF
#define MHPMEVENT_SSCOF_RESVD 16
+/* JVT CSR bits */
+#define JVT_MODE 0x3F
+#define JVT_BASE (~0x3F)
#endif
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 37b54e0991..1880e95c50 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1142,3 +1142,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+
+/* Zce helper */
+DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 55c9574299..b96c534e73 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -49,6 +49,7 @@
%uimm_cl_h 5:1 !function=ex_shift_1
%spimm 2:2 !function=ex_shift_4
%urlist 4:4
+%index 2:8
# Argument sets imported from insn32.decode:
&empty !extern
@@ -63,6 +64,7 @@
&r2_s rs1 rs2 !extern
&cmpp urlist spimm
+&cmjt index
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@@ -105,6 +107,7 @@
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
@cm_pp ... ... ........ .. &cmpp %urlist %spimm
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
+@cm_jt ... ... ........ .. &cmjt %index
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
@@ -185,7 +188,7 @@ slli 000 . ..... ..... 10 @c_shift2
sq 101 ... ... .. ... 10 @c_sqsp
c_fsd 101 ...... ..... 10 @c_sdsp
- # *** RV64 and RV32 Zcmp Extension ***
+ # *** RV64 and RV32 Zcmp/Zcmt Extension ***
[
cm_push 101 11000 .... .. 10 @cm_pp
cm_pop 101 11010 .... .. 10 @cm_pp
@@ -193,6 +196,8 @@ slli 000 . ..... ..... 10 @c_shift2
cm_popretz 101 11100 .... .. 10 @cm_pp
cm_mva01s 101 011 ... 11 ... 10 @cm_mv
cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
+
+ cm_jalt 101 000 ........ 10 @cm_jt
]
}
sw 110 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f4d5eb13f..777d7fbac0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -43,8 +43,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
/* Predicates */
#if !defined(CONFIG_USER_ONLY)
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
- uint64_t bit)
+RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
{
bool virt = riscv_cpu_virt_enabled(env);
@@ -161,6 +160,22 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
return ctr(env, csrno);
}
+static RISCVException zcmt(CPURISCVState *env, int csrno)
+{
+ if (!riscv_cpu_cfg(env)->ext_zcmt) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+#if !defined(CONFIG_USER_ONLY)
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+#endif
+
+ return RISCV_EXCP_NONE;
+}
+
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
@@ -3958,6 +3973,20 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
return ret;
}
+static RISCVException read_jvt(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->jvt;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_jvt(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ env->jvt = val;
+ return RISCV_EXCP_NONE;
+}
+
/* Control and Status Register function table */
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
@@ -3988,6 +4017,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Crypto Extension */
[CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
+ /* Zcmt Extension */
+ [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 9c455931d8..27f430ad74 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -329,6 +329,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
}
};
+static bool jvt_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+
+ return cpu->cfg.ext_zcmt;
+}
+
+static const VMStateDescription vmstate_jvt = {
+ .name = "cpu/jvt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = jvt_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.jvt, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 7,
@@ -395,6 +413,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_envcfg,
&vmstate_debug,
&vmstate_smstateen,
+ &vmstate_jvt,
NULL
}
};
diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
new file mode 100644
index 0000000000..b433bda16d
--- /dev/null
+++ b/target/riscv/zce_helper.c
@@ -0,0 +1,55 @@
+/*
+ * RISC-V Zcmt Extension Helper for QEMU.
+ *
+ * Copyright (c) 2021-2022 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
+{
+
+#if !defined(CONFIG_USER_ONLY)
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, 0);
+ }
+#endif
+
+ target_ulong target;
+ target_ulong val = env->jvt;
+ int xlen = riscv_cpu_xlen(env);
+ uint8_t mode = get_field(val, JVT_MODE);
+ target_ulong base = val & JVT_BASE;
+ target_ulong t0;
+
+ if (mode != 0) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0);
+ }
+
+ if (xlen == 32) {
+ t0 = base + (index << 2);
+ target = cpu_ldl_code(env, t0);
+ } else {
+ t0 = base + (index << 3);
+ target = cpu_ldq_code(env, t0);
+ }
+
+ return target & ~0x1;
+}
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index a47959eb67..d75acbc4a6 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zc[b,mp] Standard Extensions.
+ * RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions.
*
* Copyright (c) 2021-2022 PLCT Lab
*
@@ -26,6 +26,11 @@
return false; \
} while (0)
+#define REQUIRE_ZCMT(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcmt) \
+ return false; \
+} while (0)
+
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
{
REQUIRE_ZCB(ctx);
@@ -283,3 +288,24 @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a)
return true;
}
+
+static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
+{
+ REQUIRE_ZCMT(ctx);
+
+ /*
+ * Update pc to current for the non-unwinding exception
+ * that might come from cpu_ld*_code() in the helper.
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
+
+ /* c.jt vs c.jalt depends on the index. */
+ if (a->index >= 32) {
+ gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
+ }
+
+ tcg_gen_lookup_and_goto_ptr();
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 5dee37a242..5b7f813a3e 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,7 +19,8 @@ riscv_ss.add(files(
'bitmanip_helper.c',
'translate.c',
'm128_helper.c',
- 'crypto_helper.c'
+ 'crypto_helper.c',
+ 'zce_helper.c'
))
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 16/89] target/riscv: expose properties for Zc* extension
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2023-05-05 1:01 ` [PULL 15/89] target/riscv: add support for Zcmt extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 17/89] disas/riscv.c: add disasm support for Zc* Alistair Francis
` (74 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 97b0a77d8e..ed8dc61d10 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -87,6 +87,12 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+ ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
+ ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
+ ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
+ ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
+ ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
@@ -1491,6 +1497,14 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+
+ DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 17/89] disas/riscv.c: add disasm support for Zc*
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2023-05-05 1:01 ` [PULL 16/89] target/riscv: expose properties for Zc* extension Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 18/89] target/riscv: Add support for Zce Alistair Francis
` (73 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 227 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d6b0fbe5e8..e61bda5674 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -163,6 +163,13 @@ typedef enum {
rv_codec_v_i,
rv_codec_vsetvli,
rv_codec_vsetivli,
+ rv_codec_zcb_ext,
+ rv_codec_zcb_mul,
+ rv_codec_zcb_lb,
+ rv_codec_zcb_lh,
+ rv_codec_zcmp_cm_pushpop,
+ rv_codec_zcmp_cm_mv,
+ rv_codec_zcmt_jt,
} rv_codec;
typedef enum {
@@ -935,6 +942,26 @@ typedef enum {
rv_op_vsetvli = 766,
rv_op_vsetivli = 767,
rv_op_vsetvl = 768,
+ rv_op_c_zext_b = 769,
+ rv_op_c_sext_b = 770,
+ rv_op_c_zext_h = 771,
+ rv_op_c_sext_h = 772,
+ rv_op_c_zext_w = 773,
+ rv_op_c_not = 774,
+ rv_op_c_mul = 775,
+ rv_op_c_lbu = 776,
+ rv_op_c_lhu = 777,
+ rv_op_c_lh = 778,
+ rv_op_c_sb = 779,
+ rv_op_c_sh = 780,
+ rv_op_cm_push = 781,
+ rv_op_cm_pop = 782,
+ rv_op_cm_popret = 783,
+ rv_op_cm_popretz = 784,
+ rv_op_cm_mva01s = 785,
+ rv_op_cm_mvsa01 = 786,
+ rv_op_cm_jt = 787,
+ rv_op_cm_jalt = 788,
} rv_op;
/* structures */
@@ -958,6 +985,7 @@ typedef struct {
uint8_t rnum;
uint8_t vm;
uint32_t vzimm;
+ uint8_t rlist;
} rv_decode;
typedef struct {
@@ -1071,6 +1099,10 @@ static const char rv_vreg_name_sym[32][4] = {
#define rv_fmt_vd_vm "O\tDm"
#define rv_fmt_vsetvli "O\t0,1,v"
#define rv_fmt_vsetivli "O\t0,u,v"
+#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
+#define rv_fmt_push_rlist "O\tx,-i"
+#define rv_fmt_pop_rlist "O\tx,i"
+#define rv_fmt_zcmt_index "O\ti"
/* pseudo-instruction constraints */
@@ -2066,7 +2098,27 @@ const rv_opcode_data opcode_data[] = {
{ "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
{ "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
{ "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
+ { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
+ { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
+ { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
+ { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
+ { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
+ { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
+ { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
+ { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
+ { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
};
/* CSR names */
@@ -2085,6 +2137,7 @@ static const char *csr_name(int csrno)
case 0x000a: return "vxrm";
case 0x000f: return "vcsr";
case 0x0015: return "seed";
+ case 0x0017: return "jvt";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -2307,6 +2360,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_ld;
}
break;
+ case 4:
+ switch ((inst >> 10) & 0b111) {
+ case 0: op = rv_op_c_lbu; break;
+ case 1:
+ if (((inst >> 6) & 1) == 0) {
+ op = rv_op_c_lhu;
+ } else {
+ op = rv_op_c_lh;
+ }
+ break;
+ case 2: op = rv_op_c_sb; break;
+ case 3:
+ if (((inst >> 6) & 1) == 0) {
+ op = rv_op_c_sh;
+ }
+ break;
+ }
+ break;
case 5:
if (isa == rv128) {
op = rv_op_c_sq;
@@ -2363,6 +2434,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_c_and; break;
case 4: op = rv_op_c_subw; break;
case 5: op = rv_op_c_addw; break;
+ case 6: op = rv_op_c_mul; break;
+ case 7:
+ switch ((inst >> 2) & 0b111) {
+ case 0: op = rv_op_c_zext_b; break;
+ case 1: op = rv_op_c_sext_b; break;
+ case 2: op = rv_op_c_zext_h; break;
+ case 3: op = rv_op_c_sext_h; break;
+ case 4: op = rv_op_c_zext_w; break;
+ case 5: op = rv_op_c_not; break;
+ }
+ break;
}
break;
}
@@ -2418,6 +2500,46 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
+ if (((inst >> 12) & 0b01)) {
+ switch ((inst >> 8) & 0b01111) {
+ case 8:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_push;
+ }
+ break;
+ case 10:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_pop;
+ }
+ break;
+ case 12:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_popretz;
+ }
+ break;
+ case 14:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_popret;
+ }
+ break;
+ }
+ } else {
+ switch ((inst >> 10) & 0b011) {
+ case 0:
+ if (((inst >> 2) & 0xFF) >= 32) {
+ op = rv_op_cm_jalt;
+ } else {
+ op = rv_op_cm_jt;
+ }
+ break;
+ case 3:
+ switch ((inst >> 5) & 0b011) {
+ case 1: op = rv_op_cm_mvsa01; break;
+ case 3: op = rv_op_cm_mva01s; break;
+ }
+ break;
+ }
+ }
}
break;
case 6: op = rv_op_c_swsp; break;
@@ -3662,6 +3784,21 @@ static uint32_t operand_crs2q(rv_inst inst)
return (inst << 59) >> 61;
}
+static uint32_t calculate_xreg(uint32_t sreg)
+{
+ return sreg < 2 ? sreg + 8 : sreg + 16;
+}
+
+static uint32_t operand_sreg1(rv_inst inst)
+{
+ return calculate_xreg((inst << 54) >> 61);
+}
+
+static uint32_t operand_sreg2(rv_inst inst)
+{
+ return calculate_xreg((inst << 59) >> 61);
+}
+
static uint32_t operand_crd(rv_inst inst)
{
return (inst << 52) >> 59;
@@ -3884,6 +4021,46 @@ static uint32_t operand_vm(rv_inst inst)
return (inst << 38) >> 63;
}
+static uint32_t operand_uimm_c_lb(rv_inst inst)
+{
+ return (((inst << 58) >> 63) << 1) |
+ ((inst << 57) >> 63);
+}
+
+static uint32_t operand_uimm_c_lh(rv_inst inst)
+{
+ return (((inst << 58) >> 63) << 1);
+}
+
+static uint32_t operand_zcmp_spimm(rv_inst inst)
+{
+ return ((inst << 60) >> 62) << 4;
+}
+
+static uint32_t operand_zcmp_rlist(rv_inst inst)
+{
+ return ((inst << 56) >> 60);
+}
+
+static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
+{
+ int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
+ int regs = rlist == 15 ? 13 : rlist - 3;
+ uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
+ return stack_adj_base + spimm;
+}
+
+static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
+{
+ return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
+ operand_zcmp_spimm(inst));
+}
+
+static uint32_t operand_tbl_index(rv_inst inst)
+{
+ return ((inst << 54) >> 56);
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@@ -4200,6 +4377,34 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = operand_vimm(inst);
dec->vzimm = operand_vzimm10(inst);
break;
+ case rv_codec_zcb_lb:
+ dec->rs1 = operand_crs1q(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ dec->imm = operand_uimm_c_lb(inst);
+ break;
+ case rv_codec_zcb_lh:
+ dec->rs1 = operand_crs1q(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ dec->imm = operand_uimm_c_lh(inst);
+ break;
+ case rv_codec_zcb_ext:
+ dec->rd = operand_crs1q(inst) + 8;
+ break;
+ case rv_codec_zcb_mul:
+ dec->rd = operand_crs1rdq(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ break;
+ case rv_codec_zcmp_cm_pushpop:
+ dec->imm = operand_zcmp_stack_adj(inst, isa);
+ dec->rlist = operand_zcmp_rlist(inst);
+ break;
+ case rv_codec_zcmp_cm_mv:
+ dec->rd = operand_sreg1(inst);
+ dec->rs2 = operand_sreg2(inst);
+ break;
+ case rv_codec_zcmt_jt:
+ dec->imm = operand_tbl_index(inst);
+ break;
};
}
@@ -4359,6 +4564,9 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
+ case '-':
+ append(buf, "-", buflen);
+ break;
case 'b':
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
append(buf, tmp, buflen);
@@ -4542,6 +4750,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
append(buf, vma, buflen);
break;
}
+ case 'x': {
+ switch (dec->rlist) {
+ case 4:
+ snprintf(tmp, sizeof(tmp), "{ra}");
+ break;
+ case 5:
+ snprintf(tmp, sizeof(tmp), "{ra, s0}");
+ break;
+ case 15:
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
+ break;
+ default:
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
+ break;
+ }
+ append(buf, tmp, buflen);
+ break;
+ }
default:
break;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 18/89] target/riscv: Add support for Zce
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (16 preceding siblings ...)
2023-05-05 1:01 ` [PULL 17/89] disas/riscv.c: add disasm support for Zc* Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
` (72 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add and expose property for Zce:
* Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt.
* Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8d66365f60..5f38b0adc0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -443,6 +443,7 @@ struct RISCVCPUConfig {
bool ext_zca;
bool ext_zcb;
bool ext_zcd;
+ bool ext_zce;
bool ext_zcf;
bool ext_zcmp;
bool ext_zcmt;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ed8dc61d10..cd9e7bdce6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -91,6 +91,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce),
ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
@@ -945,6 +946,16 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
+ if (cpu->cfg.ext_zce) {
+ cpu->cfg.ext_zca = true;
+ cpu->cfg.ext_zcb = true;
+ cpu->cfg.ext_zcmp = true;
+ cpu->cfg.ext_zcmt = true;
+ if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
+ cpu->cfg.ext_zcf = true;
+ }
+ }
+
if (cpu->cfg.ext_c) {
cpu->cfg.ext_zca = true;
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
@@ -1501,6 +1512,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false),
DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 19/89] target/riscv: Fix itrigger when icount is used
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (17 preceding siblings ...)
2023-05-05 1:01 ` [PULL 18/89] target/riscv: Add support for Zce Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-07 22:22 ` Alistair Francis
2023-05-05 1:01 ` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Alistair Francis
` (71 subsequent siblings)
90 siblings, 1 reply; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, LIU Zhiwei, Weiwei Li, Alistair Francis
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
The reason is that when execute helper_mret or helper_sret, it will
cause a call to icount_get_raw_locked (), which needs set can_do_io flag
on cpustate.
Thus we setting this flag when execute these two instructions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_privileged.c.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 59501b2780..e3bee971c6 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -77,6 +77,9 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
#ifndef CONFIG_USER_ONLY
if (has_ext(ctx, RVS)) {
decode_save_opc(ctx);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_sret(cpu_pc, cpu_env);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
@@ -93,6 +96,9 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_mret(cpu_pc, cpu_env);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (18 preceding siblings ...)
2023-05-05 1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 21/89] target/riscv: Remove redundant check on RVH Alistair Francis
` (70 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
The assignment is done under the condition riscv_cpu_virt_enabled()=true.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 824f0cbd92..e140d6a8d0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1706,9 +1706,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_swap_hypervisor_regs(env);
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
env->priv);
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
- riscv_cpu_virt_enabled(env));
-
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
htval = env->guest_phys_fault_addr;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 21/89] target/riscv: Remove redundant check on RVH
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (19 preceding siblings ...)
2023-05-05 1:01 ` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Alistair Francis
` (69 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Check on riscv_cpu_virt_enabled contains the check on RVH.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 84ee018f7d..1eecae9547 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -278,8 +278,7 @@ target_ulong helper_sret(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
- if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
- get_field(env->hstatus, HSTATUS_VTSR)) {
+ if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (20 preceding siblings ...)
2023-05-05 1:01 ` [PULL 21/89] target/riscv: Remove redundant check on RVH Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Alistair Francis
` (68 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set
to true when RVH is disabled, so we can just return this bit(false) when
RVH is not disabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e140d6a8d0..62fd2c90f1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -560,10 +560,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
- if (!riscv_has_ext(env, RVH)) {
- return false;
- }
-
return get_field(env->virt, VIRT_ONOFF);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (21 preceding siblings ...)
2023-05-05 1:01 ` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Alistair Francis
` (67 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
In current implementation, riscv_cpu_set_virt_enabled is only called when
RVH is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fd2c90f1..b286118a6b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -563,12 +563,9 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env)
return get_field(env->virt, VIRT_ONOFF);
}
+/* This function can only be called to set virt when RVH is enabled */
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
{
- if (!riscv_has_ext(env, RVH)) {
- return;
- }
-
/* Flush the TLB on all virt mode changes. */
if (get_field(env->virt, VIRT_ONOFF) != enable) {
tlb_flush(env_cpu(env));
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (22 preceding siblings ...)
2023-05-05 1:01 ` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 25/89] target/riscv: Remove redundant parentheses Alistair Francis
` (66 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Weiwei Li, Alistair Francis, Richard Henderson
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu_bits.h | 3 ---
target/riscv/cpu_helper.c | 6 +++---
target/riscv/machine.c | 6 +++---
target/riscv/translate.c | 4 ++--
5 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5f38b0adc0..ff6b3c6720 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -185,7 +185,7 @@ struct CPUArchState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
- target_ulong virt;
+ bool virt_enabled;
target_ulong geilen;
uint64_t resetvec;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a92313a06f..190e517862 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -611,9 +611,6 @@ typedef enum {
#define PRV_H 2 /* Reserved */
#define PRV_M 3
-/* Virtulisation Register Fields */
-#define VIRT_ONOFF 1
-
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b286118a6b..c7bc3fc553 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -560,18 +560,18 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
- return get_field(env->virt, VIRT_ONOFF);
+ return env->virt_enabled;
}
/* This function can only be called to set virt when RVH is enabled */
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
{
/* Flush the TLB on all virt mode changes. */
- if (get_field(env->virt, VIRT_ONOFF) != enable) {
+ if (env->virt_enabled != enable) {
tlb_flush(env_cpu(env));
}
- env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+ env->virt_enabled = enable;
if (enable) {
/*
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 27f430ad74..8869346089 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -349,8 +349,8 @@ static const VMStateDescription vmstate_jvt = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 7,
- .minimum_version_id = 7,
+ .version_id = 8,
+ .minimum_version_id = 8,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -370,7 +370,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
- VMSTATE_UINTTL(env.virt, RISCVCPU),
+ VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
VMSTATE_UINT64(env.resetvec, RISCVCPU),
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
VMSTATE_UINT64(env.mstatus, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6872d17fb9..5dddac44bc 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1266,8 +1266,8 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
#ifndef CONFIG_USER_ONLY
- fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
- env->priv, env->virt);
+ fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
+ env->priv, env->virt_enabled);
#endif
target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 25/89] target/riscv: Remove redundant parentheses
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (23 preceding siblings ...)
2023-05-05 1:01 ` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 26/89] target/riscv: Fix addr type for get_physical_address Alistair Francis
` (65 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Remove redundant parentheses in get_physical_address.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c7bc3fc553..9e2be29c45 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1051,7 +1051,7 @@ restart:
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
*prot |= PAGE_READ;
}
- if ((pte & PTE_X)) {
+ if (pte & PTE_X) {
*prot |= PAGE_EXEC;
}
/* add write permission on stores or if the page is already dirty,
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 26/89] target/riscv: Fix addr type for get_physical_address
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (24 preceding siblings ...)
2023-05-05 1:01 ` [PULL 25/89] target/riscv: Remove redundant parentheses Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Alistair Francis
` (64 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Richard Henderson
From: Weiwei Li <liweiwei@iscas.ac.cn>
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9e2be29c45..b0e094a933 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -732,7 +732,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
* @env: CPURISCVState
* @physical: This will be set to the calculated physical address
* @prot: The returned protection attributes
- * @addr: The virtual address to be translated
+ * @addr: The virtual address or guest physical address to be translated
* @fault_pte_addr: If not NULL, this will be set to fault pte address
* when a error occurs on pte address translation.
* This will already be shifted to match htval.
@@ -744,7 +744,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
* @is_debug: Is this access from a debugger or the monitor?
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
- int *prot, target_ulong addr,
+ int *prot, vaddr addr,
target_ulong *fault_pte_addr,
int access_type, int mmu_idx,
bool first_stage, bool two_stage,
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (25 preceding siblings ...)
2023-05-05 1:01 ` [PULL 26/89] target/riscv: Fix addr type for get_physical_address Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Alistair Francis
` (63 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (26 preceding siblings ...)
2023-05-05 1:01 ` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 29/89] target/riscv: Fix format for indentation Alistair Francis
` (62 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, LIU Zhiwei, Junqiang Wang,
Richard Henderson, Alistair Francis, Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Directly use env->virt_enabled instead.
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 51 ++++++++++++++++++---------------------
target/riscv/csr.c | 46 +++++++++++++++++------------------
target/riscv/debug.c | 10 ++++----
target/riscv/op_helper.c | 18 +++++++-------
target/riscv/pmu.c | 4 +--
target/riscv/translate.c | 2 +-
8 files changed, 64 insertions(+), 70 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ff6b3c6720..995192757a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -585,7 +585,6 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env);
target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
-bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cd9e7bdce6..c304deabd7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,7 +556,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
+ qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
}
#endif
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b0e094a933..fbcdec3c06 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -93,8 +93,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVH)) {
if (env->priv == PRV_M ||
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ (env->priv == PRV_S && !env->virt_enabled) ||
+ (env->priv == PRV_U && !env->virt_enabled &&
get_field(env->hstatus, HSTATUS_HU))) {
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
@@ -391,7 +391,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
uint64_t irqs, pending, mie, hsie, vsie;
/* Determine interrupt enable state of all privilege modes */
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
mie = 1;
hsie = 1;
vsie = (env->priv < PRV_S) ||
@@ -452,7 +452,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
- if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
+ if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
return false;
}
return true;
@@ -465,7 +465,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
bool riscv_cpu_vector_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_VS) {
- if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+ if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
return false;
}
return true;
@@ -483,7 +483,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
if (riscv_has_ext(env, RVF)) {
mstatus_mask |= MSTATUS_FS;
}
- bool current_virt = riscv_cpu_virt_enabled(env);
+ bool current_virt = env->virt_enabled;
g_assert(riscv_has_ext(env, RVH));
@@ -558,11 +558,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
env->geilen = geilen;
}
-bool riscv_cpu_virt_enabled(CPURISCVState *env)
-{
- return env->virt_enabled;
-}
-
/* This function can only be called to set virt when RVH is enabled */
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
{
@@ -609,7 +604,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
CPUState *cs = env_cpu(env);
uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
gein = get_field(env->hstatus, HSTATUS_VGEIN);
vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
}
@@ -768,7 +763,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
- if (!riscv_cpu_virt_enabled(env) && two_stage) {
+ if (!env->virt_enabled && two_stage) {
use_background = true;
}
@@ -931,7 +926,7 @@ restart:
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
bool hade = env->menvcfg & MENVCFG_HADE;
- if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
+ if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
hade = hade && (env->henvcfg & HENVCFG_HADE);
}
@@ -1091,7 +1086,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
switch (access_type) {
case MMU_INST_FETCH:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if (env->virt_enabled && !first_stage) {
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -1131,11 +1126,11 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
- true, riscv_cpu_virt_enabled(env), true)) {
+ true, env->virt_enabled, true)) {
return -1;
}
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
0, mmu_idx, false, true, true)) {
return -1;
@@ -1163,7 +1158,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
}
env->badaddr = addr;
- env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+ env->two_stage_lookup = env->virt_enabled ||
riscv_cpu_two_stage_lookup(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
@@ -1189,7 +1184,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
+ env->two_stage_lookup = env->virt_enabled ||
riscv_cpu_two_stage_lookup(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
@@ -1253,7 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
pmu_tlb_fill_incr_ctr(cpu, access_type);
- if (riscv_cpu_virt_enabled(env) ||
+ if (env->virt_enabled ||
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
@@ -1351,7 +1346,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else {
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
- riscv_cpu_virt_enabled(env) ||
+ env->virt_enabled ||
riscv_cpu_two_stage_lookup(mmu_idx),
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
@@ -1658,9 +1653,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (env->priv == PRV_M) {
cause = RISCV_EXCP_M_ECALL;
- } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+ } else if (env->priv == PRV_S && env->virt_enabled) {
cause = RISCV_EXCP_VS_ECALL;
- } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
+ } else if (env->priv == PRV_S && !env->virt_enabled) {
cause = RISCV_EXCP_S_ECALL;
} else if (env->priv == PRV_U) {
cause = RISCV_EXCP_U_ECALL;
@@ -1683,7 +1678,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_has_ext(env, RVH)) {
uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
- if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
+ if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
/* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
@@ -1694,7 +1689,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause = cause - 1;
}
write_gva = false;
- } else if (riscv_cpu_virt_enabled(env)) {
+ } else if (env->virt_enabled) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
@@ -1728,12 +1723,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
} else {
/* handle the trap in M-mode */
if (riscv_has_ext(env, RVH)) {
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
riscv_cpu_swap_hypervisor_regs(env);
}
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
- riscv_cpu_virt_enabled(env));
- if (riscv_cpu_virt_enabled(env) && tval) {
+ env->virt_enabled);
+ if (env->virt_enabled && tval) {
env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 777d7fbac0..41e56012d5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -45,7 +45,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
#if !defined(CONFIG_USER_ONLY)
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_NONE;
@@ -135,7 +135,7 @@ skip_ext_pmu_check:
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (!get_field(env->hcounteren, ctr_mask) ||
(env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -365,7 +365,7 @@ static RISCVException hstateenh(CPURISCVState *env, int csrno)
static RISCVException sstateen(CPURISCVState *env, int csrno)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
if (!riscv_cpu_cfg(env)->ext_smstateen) {
@@ -430,7 +430,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -536,7 +536,7 @@ static RISCVException seed(CPURISCVState *env, int csrno)
*/
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
- } else if (riscv_cpu_virt_enabled(env)) {
+ } else if (env->virt_enabled) {
if (env->mseccfg & MSECCFG_SSEED) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} else {
@@ -964,7 +964,7 @@ static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
{
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -977,7 +977,7 @@ static RISCVException read_time(CPURISCVState *env, int csrno,
static RISCVException read_timeh(CPURISCVState *env, int csrno,
target_ulong *val)
{
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -1031,7 +1031,7 @@ static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
*val = env->vstimecmp;
} else {
*val = env->stimecmp;
@@ -1043,7 +1043,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
*val = env->vstimecmp >> 32;
} else {
*val = env->stimecmp >> 32;
@@ -1055,7 +1055,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
@@ -1076,7 +1076,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
@@ -1530,7 +1530,7 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_virt_enabled(env)) {
+ if (!env->virt_enabled) {
return csrno;
}
@@ -1687,7 +1687,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
done:
if (ret) {
- return (riscv_cpu_virt_enabled(env) && virt) ?
+ return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
@@ -1741,7 +1741,7 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
done:
if (ret) {
- return (riscv_cpu_virt_enabled(env) && virt) ?
+ return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
@@ -2171,7 +2171,7 @@ static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
static RISCVException read_sstateen(CPURISCVState *env, int csrno,
target_ulong *val)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
*val = env->sstateen[index] & env->mstateen[index];
@@ -2185,7 +2185,7 @@ static RISCVException read_sstateen(CPURISCVState *env, int csrno,
static RISCVException write_sstateen(CPURISCVState *env, int csrno,
uint64_t mask, target_ulong new_val)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
uint64_t wr_mask;
uint64_t *reg;
@@ -2380,7 +2380,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
RISCVException ret;
uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
@@ -2590,7 +2590,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
RISCVException ret;
uint64_t mask = env->mideleg & sip_writable_mask;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
@@ -2783,7 +2783,7 @@ static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
int irq;
uint8_t iprio;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
return read_vstopi(env, CSR_VSTOPI, val);
}
@@ -3128,7 +3128,7 @@ static int read_hvipriox(CPURISCVState *env, int first_index,
/* First index has to be a multiple of number of irqs per register */
if (first_index % num_irqs) {
- return (riscv_cpu_virt_enabled(env)) ?
+ return (env->virt_enabled) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
@@ -3154,7 +3154,7 @@ static int write_hvipriox(CPURISCVState *env, int first_index,
/* First index has to be a multiple of number of irqs per register */
if (first_index % num_irqs) {
- return (riscv_cpu_virt_enabled(env)) ?
+ return (env->virt_enabled) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
@@ -3809,7 +3809,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csr_priv, effective_priv = env->priv;
if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env)) {
+ !env->virt_enabled) {
/*
* We are in HS mode. Add 1 to the effective privledge level to
* allow us to access the Hypervisor CSRs.
@@ -3819,7 +3819,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
csr_priv = get_field(csrno, 0x300);
if (!env->debugger && (effective_priv < csr_priv)) {
- if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+ if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index b091293069..1f7aed23c9 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int value)
static bool check_itrigger_priv(CPURISCVState *env, int index)
{
target_ulong tdata1 = env->tdata1[index];
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
(get_field(tdata1, ITRIGGER_VU) == env->priv);
@@ -787,7 +787,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
return false;
}
@@ -806,7 +806,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
pc = env->tdata2[i];
if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
if ((ctrl >> 23) & BIT(env->priv)) {
return true;
@@ -845,7 +845,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
return false;
}
@@ -880,7 +880,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
}
if ((wp->flags & flags) && (wp->vaddr == addr)) {
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
if ((ctrl >> 23) & BIT(env->priv)) {
return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1eecae9547..c0c4ced7f0 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -140,7 +140,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
- if (riscv_cpu_virt_enabled(env) &&
+ if (env->virt_enabled &&
(((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
@@ -278,7 +278,7 @@ target_ulong helper_sret(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
- if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) {
+ if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
}
@@ -293,7 +293,7 @@ target_ulong helper_sret(CPURISCVState *env)
}
env->mstatus = mstatus;
- if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
+ if (riscv_has_ext(env, RVH) && !env->virt_enabled) {
/* We support Hypervisor extensions and virtulisation is disabled */
target_ulong hstatus = env->hstatus;
@@ -365,9 +365,9 @@ void helper_wfi(CPURISCVState *env)
bool prv_s = env->priv == PRV_S;
if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
- (rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
+ (rvs && prv_u && !env->virt_enabled)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
- } else if (riscv_cpu_virt_enabled(env) && (prv_u ||
+ } else if (env->virt_enabled && (prv_u ||
(prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
@@ -384,7 +384,7 @@ void helper_tlb_flush(CPURISCVState *env)
(env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
- } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ } else if (riscv_has_ext(env, RVH) && env->virt_enabled &&
get_field(env->hstatus, HSTATUS_VTVM)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
@@ -402,12 +402,12 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
- if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+ if (env->priv == PRV_S && env->virt_enabled) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
}
if (env->priv == PRV_M ||
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
+ (env->priv == PRV_S && !env->virt_enabled)) {
tlb_flush(cs);
return;
}
@@ -417,7 +417,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
{
- if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
+ if (env->priv == PRV_S && !env->virt_enabled &&
get_field(env->mstatus, MSTATUS_TVM)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 96ce2dbe49..48ad60be2b 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -109,7 +109,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
CPURISCVState *env = &cpu->env;
target_ulong max_val = UINT32_MAX;
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
- bool virt_on = riscv_cpu_virt_enabled(env);
+ bool virt_on = env->virt_enabled;
/* Privilege mode filtering */
if ((env->priv == PRV_M &&
@@ -150,7 +150,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
CPURISCVState *env = &cpu->env;
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
uint64_t max_val = UINT64_MAX;
- bool virt_on = riscv_cpu_virt_enabled(env);
+ bool virt_on = env->virt_enabled;
/* Privilege mode filtering */
if ((env->priv == PRV_M &&
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5dddac44bc..03748f72e6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1169,7 +1169,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
- ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+ ctx->virt_enabled = env->virt_enabled;
} else {
ctx->virt_enabled = false;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 29/89] target/riscv: Fix format for indentation
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (27 preceding siblings ...)
2023-05-05 1:01 ` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 30/89] target/riscv: Fix format for comments Alistair Francis
` (61 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei,
Alistair Francis, Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.h | 9 +-
target/riscv/arch_dump.c | 4 +-
target/riscv/cpu.c | 40 +++---
target/riscv/cpu_helper.c | 163 ++++++++++++------------
target/riscv/fpu_helper.c | 24 ++--
target/riscv/m128_helper.c | 16 +--
target/riscv/machine.c | 18 +--
target/riscv/op_helper.c | 4 +-
target/riscv/pmp.c | 19 +--
target/riscv/translate.c | 4 +-
target/riscv/vector_helper.c | 159 +++++++++++------------
target/riscv/insn_trans/trans_rvv.c.inc | 28 ++--
12 files changed, 247 insertions(+), 241 deletions(-)
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index da32c61c85..b296ea1fc6 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -63,18 +63,19 @@ typedef struct {
} pmp_table_t;
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
- target_ulong val);
+ target_ulong val);
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
target_ulong mseccfg_csr_read(CPURISCVState *env);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
- target_ulong val);
+ target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
- target_ulong mode);
+ target_ulong size, pmp_priv_t privs,
+ pmp_priv_t *allowed_privs,
+ target_ulong mode);
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
index 736a232956..573587810e 100644
--- a/target/riscv/arch_dump.c
+++ b/target/riscv/arch_dump.c
@@ -180,8 +180,8 @@ int cpu_get_dump_info(ArchDumpInfo *info,
info->d_class = ELFCLASS32;
#endif
- info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
- ? ELFDATA2MSB : ELFDATA2LSB;
+ info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 ?
+ ELFDATA2MSB : ELFDATA2LSB;
return 0;
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c304deabd7..8ed8601399 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -54,7 +54,7 @@ struct isa_ext_data {
};
#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
-{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+ {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
/**
* Here are the ordering rules of extension naming defined by RISC-V
@@ -157,29 +157,29 @@ static void isa_ext_update_enabled(RISCVCPU *cpu,
}
const char * const riscv_int_regnames[] = {
- "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
- "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
- "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
- "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
- "x28/t3", "x29/t4", "x30/t5", "x31/t6"
+ "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
+ "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
+ "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
+ "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
+ "x28/t3", "x29/t4", "x30/t5", "x31/t6"
};
const char * const riscv_int_regnamesh[] = {
- "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
- "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
- "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
- "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
- "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
- "x30h/t5h", "x31h/t6h"
+ "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
+ "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
+ "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
+ "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
+ "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
+ "x30h/t5h", "x31h/t6h"
};
const char * const riscv_fpr_regnames[] = {
- "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
- "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
- "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
- "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
- "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
- "f30/ft10", "f31/ft11"
+ "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
+ "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
+ "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
+ "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
+ "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
+ "f30/ft10", "f31/ft11"
};
static const char * const riscv_excp_names[] = {
@@ -351,8 +351,8 @@ static void riscv_any_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj),
- riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
- VM_1_10_SV32 : VM_1_10_SV57);
+ riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
+ VM_1_10_SV32 : VM_1_10_SV57);
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fbcdec3c06..8d2547a164 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,12 +68,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ FIELD_EX64(env->vtype, VTYPE, VLMUL));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
flags = FIELD_DP32(flags, TB_FLAGS, VTA,
- FIELD_EX64(env->vtype, VTYPE, VTA));
+ FIELD_EX64(env->vtype, VTYPE, VTA));
flags = FIELD_DP32(flags, TB_FLAGS, VMA,
- FIELD_EX64(env->vtype, VTYPE, VMA));
+ FIELD_EX64(env->vtype, VTYPE, VMA));
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
}
@@ -95,7 +95,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (env->priv == PRV_M ||
(env->priv == PRV_S && !env->virt_enabled) ||
(env->priv == PRV_U && !env->virt_enabled &&
- get_field(env->hstatus, HSTATUS_HU))) {
+ get_field(env->hstatus, HSTATUS_HU))) {
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
@@ -230,75 +230,75 @@ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
* ----------------------------------------------------------------
*/
static const uint8_t default_iprio[64] = {
- /* Custom interrupts 48 to 63 */
- [63] = IPRIO_MMAXIPRIO,
- [62] = IPRIO_MMAXIPRIO,
- [61] = IPRIO_MMAXIPRIO,
- [60] = IPRIO_MMAXIPRIO,
- [59] = IPRIO_MMAXIPRIO,
- [58] = IPRIO_MMAXIPRIO,
- [57] = IPRIO_MMAXIPRIO,
- [56] = IPRIO_MMAXIPRIO,
- [55] = IPRIO_MMAXIPRIO,
- [54] = IPRIO_MMAXIPRIO,
- [53] = IPRIO_MMAXIPRIO,
- [52] = IPRIO_MMAXIPRIO,
- [51] = IPRIO_MMAXIPRIO,
- [50] = IPRIO_MMAXIPRIO,
- [49] = IPRIO_MMAXIPRIO,
- [48] = IPRIO_MMAXIPRIO,
-
- /* Custom interrupts 24 to 31 */
- [31] = IPRIO_MMAXIPRIO,
- [30] = IPRIO_MMAXIPRIO,
- [29] = IPRIO_MMAXIPRIO,
- [28] = IPRIO_MMAXIPRIO,
- [27] = IPRIO_MMAXIPRIO,
- [26] = IPRIO_MMAXIPRIO,
- [25] = IPRIO_MMAXIPRIO,
- [24] = IPRIO_MMAXIPRIO,
-
- [47] = IPRIO_DEFAULT_UPPER,
- [23] = IPRIO_DEFAULT_UPPER + 1,
- [46] = IPRIO_DEFAULT_UPPER + 2,
- [45] = IPRIO_DEFAULT_UPPER + 3,
- [22] = IPRIO_DEFAULT_UPPER + 4,
- [44] = IPRIO_DEFAULT_UPPER + 5,
-
- [43] = IPRIO_DEFAULT_UPPER + 6,
- [21] = IPRIO_DEFAULT_UPPER + 7,
- [42] = IPRIO_DEFAULT_UPPER + 8,
- [41] = IPRIO_DEFAULT_UPPER + 9,
- [20] = IPRIO_DEFAULT_UPPER + 10,
- [40] = IPRIO_DEFAULT_UPPER + 11,
-
- [11] = IPRIO_DEFAULT_M,
- [3] = IPRIO_DEFAULT_M + 1,
- [7] = IPRIO_DEFAULT_M + 2,
-
- [9] = IPRIO_DEFAULT_S,
- [1] = IPRIO_DEFAULT_S + 1,
- [5] = IPRIO_DEFAULT_S + 2,
-
- [12] = IPRIO_DEFAULT_SGEXT,
-
- [10] = IPRIO_DEFAULT_VS,
- [2] = IPRIO_DEFAULT_VS + 1,
- [6] = IPRIO_DEFAULT_VS + 2,
-
- [39] = IPRIO_DEFAULT_LOWER,
- [19] = IPRIO_DEFAULT_LOWER + 1,
- [38] = IPRIO_DEFAULT_LOWER + 2,
- [37] = IPRIO_DEFAULT_LOWER + 3,
- [18] = IPRIO_DEFAULT_LOWER + 4,
- [36] = IPRIO_DEFAULT_LOWER + 5,
-
- [35] = IPRIO_DEFAULT_LOWER + 6,
- [17] = IPRIO_DEFAULT_LOWER + 7,
- [34] = IPRIO_DEFAULT_LOWER + 8,
- [33] = IPRIO_DEFAULT_LOWER + 9,
- [16] = IPRIO_DEFAULT_LOWER + 10,
- [32] = IPRIO_DEFAULT_LOWER + 11,
+ /* Custom interrupts 48 to 63 */
+ [63] = IPRIO_MMAXIPRIO,
+ [62] = IPRIO_MMAXIPRIO,
+ [61] = IPRIO_MMAXIPRIO,
+ [60] = IPRIO_MMAXIPRIO,
+ [59] = IPRIO_MMAXIPRIO,
+ [58] = IPRIO_MMAXIPRIO,
+ [57] = IPRIO_MMAXIPRIO,
+ [56] = IPRIO_MMAXIPRIO,
+ [55] = IPRIO_MMAXIPRIO,
+ [54] = IPRIO_MMAXIPRIO,
+ [53] = IPRIO_MMAXIPRIO,
+ [52] = IPRIO_MMAXIPRIO,
+ [51] = IPRIO_MMAXIPRIO,
+ [50] = IPRIO_MMAXIPRIO,
+ [49] = IPRIO_MMAXIPRIO,
+ [48] = IPRIO_MMAXIPRIO,
+
+ /* Custom interrupts 24 to 31 */
+ [31] = IPRIO_MMAXIPRIO,
+ [30] = IPRIO_MMAXIPRIO,
+ [29] = IPRIO_MMAXIPRIO,
+ [28] = IPRIO_MMAXIPRIO,
+ [27] = IPRIO_MMAXIPRIO,
+ [26] = IPRIO_MMAXIPRIO,
+ [25] = IPRIO_MMAXIPRIO,
+ [24] = IPRIO_MMAXIPRIO,
+
+ [47] = IPRIO_DEFAULT_UPPER,
+ [23] = IPRIO_DEFAULT_UPPER + 1,
+ [46] = IPRIO_DEFAULT_UPPER + 2,
+ [45] = IPRIO_DEFAULT_UPPER + 3,
+ [22] = IPRIO_DEFAULT_UPPER + 4,
+ [44] = IPRIO_DEFAULT_UPPER + 5,
+
+ [43] = IPRIO_DEFAULT_UPPER + 6,
+ [21] = IPRIO_DEFAULT_UPPER + 7,
+ [42] = IPRIO_DEFAULT_UPPER + 8,
+ [41] = IPRIO_DEFAULT_UPPER + 9,
+ [20] = IPRIO_DEFAULT_UPPER + 10,
+ [40] = IPRIO_DEFAULT_UPPER + 11,
+
+ [11] = IPRIO_DEFAULT_M,
+ [3] = IPRIO_DEFAULT_M + 1,
+ [7] = IPRIO_DEFAULT_M + 2,
+
+ [9] = IPRIO_DEFAULT_S,
+ [1] = IPRIO_DEFAULT_S + 1,
+ [5] = IPRIO_DEFAULT_S + 2,
+
+ [12] = IPRIO_DEFAULT_SGEXT,
+
+ [10] = IPRIO_DEFAULT_VS,
+ [2] = IPRIO_DEFAULT_VS + 1,
+ [6] = IPRIO_DEFAULT_VS + 2,
+
+ [39] = IPRIO_DEFAULT_LOWER,
+ [19] = IPRIO_DEFAULT_LOWER + 1,
+ [38] = IPRIO_DEFAULT_LOWER + 2,
+ [37] = IPRIO_DEFAULT_LOWER + 3,
+ [18] = IPRIO_DEFAULT_LOWER + 4,
+ [36] = IPRIO_DEFAULT_LOWER + 5,
+
+ [35] = IPRIO_DEFAULT_LOWER + 6,
+ [17] = IPRIO_DEFAULT_LOWER + 7,
+ [34] = IPRIO_DEFAULT_LOWER + 8,
+ [33] = IPRIO_DEFAULT_LOWER + 9,
+ [16] = IPRIO_DEFAULT_LOWER + 10,
+ [32] = IPRIO_DEFAULT_LOWER + 11,
};
uint8_t riscv_cpu_default_priority(int irq)
@@ -1001,8 +1001,8 @@ restart:
*/
MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1;
- mr = address_space_translate(cs->as, pte_addr,
- &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
+ mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
+ false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -1052,7 +1052,7 @@ restart:
/* add write permission on stores or if the page is already dirty,
so that we TLB miss on later writes to update the dirty bit */
if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
@@ -1281,9 +1281,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
false);
qemu_log_mask(CPU_LOG_MMU,
- "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
- HWADDR_FMT_plx " prot %d\n",
- __func__, im_address, ret, pa, prot2);
+ "%s 2nd-stage address=%" VADDR_PRIx
+ " ret %d physical "
+ HWADDR_FMT_plx " prot %d\n",
+ __func__, im_address, ret, pa, prot2);
prot &= prot2;
@@ -1718,7 +1719,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->htval = htval;
env->htinst = tinst;
env->pc = (env->stvec >> 2 << 2) +
- ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
+ ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* handle the trap in M-mode */
@@ -1749,7 +1750,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mtval2 = mtval2;
env->mtinst = tinst;
env->pc = (env->mtvec >> 2 << 2) +
- ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
+ ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M);
}
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 449d236df6..5dd14d8390 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -248,8 +248,8 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float32 frs1 = check_nanbox_s(env, rs1);
float32 frs2 = check_nanbox_s(env, rs2);
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
- float32_minnum(frs1, frs2, &env->fp_status) :
- float32_minimum_number(frs1, frs2, &env->fp_status));
+ float32_minnum(frs1, frs2, &env->fp_status) :
+ float32_minimum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
@@ -257,8 +257,8 @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float32 frs1 = check_nanbox_s(env, rs1);
float32 frs2 = check_nanbox_s(env, rs2);
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
- float32_maxnum(frs1, frs2, &env->fp_status) :
- float32_maximum_number(frs1, frs2, &env->fp_status));
+ float32_maxnum(frs1, frs2, &env->fp_status) :
+ float32_maximum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
@@ -361,15 +361,15 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return env->priv_ver < PRIV_VERSION_1_11_0 ?
- float64_minnum(frs1, frs2, &env->fp_status) :
- float64_minimum_number(frs1, frs2, &env->fp_status);
+ float64_minnum(frs1, frs2, &env->fp_status) :
+ float64_minimum_number(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return env->priv_ver < PRIV_VERSION_1_11_0 ?
- float64_maxnum(frs1, frs2, &env->fp_status) :
- float64_maximum_number(frs1, frs2, &env->fp_status);
+ float64_maxnum(frs1, frs2, &env->fp_status) :
+ float64_maximum_number(frs1, frs2, &env->fp_status);
}
uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
@@ -481,8 +481,8 @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs2 = check_nanbox_h(env, rs2);
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
- float16_minnum(frs1, frs2, &env->fp_status) :
- float16_minimum_number(frs1, frs2, &env->fp_status));
+ float16_minnum(frs1, frs2, &env->fp_status) :
+ float16_minimum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
@@ -490,8 +490,8 @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs2 = check_nanbox_h(env, rs2);
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
- float16_maxnum(frs1, frs2, &env->fp_status) :
- float16_maximum_number(frs1, frs2, &env->fp_status));
+ float16_maxnum(frs1, frs2, &env->fp_status) :
+ float16_maximum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c
index 7bf115b85e..e6a4f6120a 100644
--- a/target/riscv/m128_helper.c
+++ b/target/riscv/m128_helper.c
@@ -24,8 +24,8 @@
#include "exec/helper-proto.h"
target_ulong HELPER(divu_i128)(CPURISCVState *env,
- target_ulong ul, target_ulong uh,
- target_ulong vl, target_ulong vh)
+ target_ulong ul, target_ulong uh,
+ target_ulong vl, target_ulong vh)
{
target_ulong ql, qh;
Int128 q;
@@ -44,8 +44,8 @@ target_ulong HELPER(divu_i128)(CPURISCVState *env,
}
target_ulong HELPER(remu_i128)(CPURISCVState *env,
- target_ulong ul, target_ulong uh,
- target_ulong vl, target_ulong vh)
+ target_ulong ul, target_ulong uh,
+ target_ulong vl, target_ulong vh)
{
target_ulong rl, rh;
Int128 r;
@@ -64,8 +64,8 @@ target_ulong HELPER(remu_i128)(CPURISCVState *env,
}
target_ulong HELPER(divs_i128)(CPURISCVState *env,
- target_ulong ul, target_ulong uh,
- target_ulong vl, target_ulong vh)
+ target_ulong ul, target_ulong uh,
+ target_ulong vl, target_ulong vh)
{
target_ulong qh, ql;
Int128 q;
@@ -89,8 +89,8 @@ target_ulong HELPER(divs_i128)(CPURISCVState *env,
}
target_ulong HELPER(rems_i128)(CPURISCVState *env,
- target_ulong ul, target_ulong uh,
- target_ulong vl, target_ulong vh)
+ target_ulong ul, target_ulong uh,
+ target_ulong vl, target_ulong vh)
{
target_ulong rh, rl;
Int128 r;
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 8869346089..3ce2970785 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -136,15 +136,15 @@ static const VMStateDescription vmstate_vector = {
.minimum_version_id = 2,
.needed = vector_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
- VMSTATE_UINTTL(env.vxrm, RISCVCPU),
- VMSTATE_UINTTL(env.vxsat, RISCVCPU),
- VMSTATE_UINTTL(env.vl, RISCVCPU),
- VMSTATE_UINTTL(env.vstart, RISCVCPU),
- VMSTATE_UINTTL(env.vtype, RISCVCPU),
- VMSTATE_BOOL(env.vill, RISCVCPU),
- VMSTATE_END_OF_LIST()
- }
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
};
static bool pointermasking_needed(void *opaque)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index c0c4ced7f0..ec9a384772 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -367,8 +367,8 @@ void helper_wfi(CPURISCVState *env)
if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
(rvs && prv_u && !env->virt_enabled)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
- } else if (env->virt_enabled && (prv_u ||
- (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
+ } else if (env->virt_enabled &&
+ (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
cs->halted = 1;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index a08cd95658..3943b0f2e3 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -27,7 +27,7 @@
#include "exec/exec-all.h"
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
- uint8_t val);
+ uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
@@ -220,8 +220,8 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{
int result = 0;
- if ((addr >= env->pmp_state.addr[pmp_index].sa)
- && (addr <= env->pmp_state.addr[pmp_index].ea)) {
+ if ((addr >= env->pmp_state.addr[pmp_index].sa) &&
+ (addr <= env->pmp_state.addr[pmp_index].ea)) {
result = 1;
} else {
result = 0;
@@ -234,8 +234,9 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
* Check if the address has required RWX privs when no PMP entry is matched.
*/
static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
- target_ulong mode)
+ target_ulong size, pmp_priv_t privs,
+ pmp_priv_t *allowed_privs,
+ target_ulong mode)
{
bool ret;
@@ -297,8 +298,8 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
* Return negtive value if no match
*/
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
- target_ulong mode)
+ target_ulong size, pmp_priv_t privs,
+ pmp_priv_t *allowed_privs, target_ulong mode)
{
int i = 0;
int ret = -1;
@@ -466,7 +467,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
* Handle a write to a pmpcfg CSR
*/
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
- target_ulong val)
+ target_ulong val)
{
int i;
uint8_t cfg_val;
@@ -508,7 +509,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
* Handle a write to a pmpaddr CSR
*/
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
- target_ulong val)
+ target_ulong val)
{
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 03748f72e6..3613aca28d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -746,8 +746,8 @@ EX_SH(12)
} while (0)
#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
- if (!ctx->cfg_ptr->ext_##A && \
- !ctx->cfg_ptr->ext_##B) { \
+ if (!ctx->cfg_ptr->ext_##A && \
+ !ctx->cfg_ptr->ext_##B) { \
return false; \
} \
} while (0)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2423affe37..6067b5cfc7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -50,10 +50,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
}
}
- if ((sew > cpu->cfg.elen)
- || vill
- || (ediv != 0)
- || (reserved != 0)) {
+ if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
env->vill = 1;
env->vtype = 0;
@@ -1116,7 +1113,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
- env->vstart = 0; \
+ env->vstart = 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
@@ -1308,7 +1305,8 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* generate the helpers for shift instructions with one vector and one scalar */
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
@@ -1735,9 +1733,9 @@ GEN_VEXT_VX(vmulhsu_vx_d, 8)
/* Vector Integer Divide Instructions */
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
-#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
+#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
-#define DO_REM(N, M) (unlikely(M == 0) ? N :\
+#define DO_REM(N, M) (unlikely(M == 0) ? N : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
@@ -1846,7 +1844,7 @@ GEN_VEXT_VX(vwmulsu_vx_h, 4)
GEN_VEXT_VX(vwmulsu_vx_w, 8)
/* Vector Single-Width Integer Multiply-Add Instructions */
-#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
+#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
{ \
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
@@ -2277,7 +2275,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
/* generate helpers for fixed point instructions with OPIVX format */
#define GEN_VEXT_VX_RM(NAME, ESZ) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \
do_##NAME, ESZ); \
@@ -2651,7 +2650,7 @@ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
res = (int16_t)a * (int16_t)b;
round = get_round(vxrm, res, 7);
- res = (res >> 7) + round;
+ res = (res >> 7) + round;
if (res > INT8_MAX) {
env->vxsat = 0x1;
@@ -2671,7 +2670,7 @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
res = (int32_t)a * (int32_t)b;
round = get_round(vxrm, res, 15);
- res = (res >> 15) + round;
+ res = (res >> 15) + round;
if (res > INT16_MAX) {
env->vxsat = 0x1;
@@ -2691,7 +2690,7 @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
res = (int64_t)a * (int64_t)b;
round = get_round(vxrm, res, 31);
- res = (res >> 31) + round;
+ res = (res >> 31) + round;
if (res > INT32_MAX) {
env->vxsat = 0x1;
@@ -2758,7 +2757,7 @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
uint8_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
return res;
}
static inline uint16_t
@@ -2862,7 +2861,7 @@ vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b)
int16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT8_MAX) {
env->vxsat = 0x1;
return INT8_MAX;
@@ -2881,7 +2880,7 @@ vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b)
int32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT16_MAX) {
env->vxsat = 0x1;
return INT16_MAX;
@@ -2900,7 +2899,7 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
int64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT32_MAX) {
env->vxsat = 0x1;
return INT32_MAX;
@@ -2933,7 +2932,7 @@ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
uint16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT8_MAX) {
env->vxsat = 0x1;
return UINT8_MAX;
@@ -2949,7 +2948,7 @@ vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b)
uint32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT16_MAX) {
env->vxsat = 0x1;
return UINT16_MAX;
@@ -2965,7 +2964,7 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
uint64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT32_MAX) {
env->vxsat = 0x1;
return UINT32_MAX;
@@ -3052,7 +3051,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t total_elems = \
- vext_get_total_elems(env, desc, ESZ); \
+ vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -3118,13 +3117,13 @@ GEN_VEXT_VF(vfrsub_vf_d, 8)
static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
{
return float32_add(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
{
return float64_add(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
@@ -3140,13 +3139,13 @@ GEN_VEXT_VF(vfwadd_vf_w, 8)
static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
{
return float32_sub(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
{
return float64_sub(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
@@ -3250,13 +3249,13 @@ GEN_VEXT_VF(vfrdiv_vf_d, 8)
static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
{
return float32_mul(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
{
return float64_mul(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
@@ -3271,7 +3270,7 @@ GEN_VEXT_VF(vfwmul_vf_w, 8)
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
#define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
@@ -3303,7 +3302,7 @@ GEN_VEXT_VV_ENV(vfmacc_vv_d, 8)
#define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
TD d = *((TD *)vd + HD(i)); \
@@ -3319,20 +3318,20 @@ GEN_VEXT_VF(vfmacc_vf_d, 8)
static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
- return float16_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float16_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
- return float32_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float32_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
- return float64_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
@@ -3434,20 +3433,20 @@ GEN_VEXT_VF(vfmadd_vf_d, 8)
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
- return float16_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float16_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
- return float32_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float32_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
- return float64_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
@@ -3523,13 +3522,13 @@ GEN_VEXT_VF(vfnmsub_vf_d, 8)
static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d, 0, s);
+ float16_to_float32(b, true, s), d, 0, s);
}
static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d, 0, s);
+ float32_to_float64(b, s), d, 0, s);
}
RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
@@ -3544,15 +3543,16 @@ GEN_VEXT_VF(vfwmacc_vf_w, 8)
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_c | float_muladd_negate_product,
+ s);
}
static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
- return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, s),
+ d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
@@ -3567,15 +3567,15 @@ GEN_VEXT_VF(vfwnmacc_vf_w, 8)
static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_c, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_c, s);
}
static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_c, s);
+ float32_to_float64(b, s), d,
+ float_muladd_negate_c, s);
}
RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
@@ -3590,15 +3590,15 @@ GEN_VEXT_VF(vfwmsac_vf_w, 8)
static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_product, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_product, s);
}
static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_product, s);
+ float32_to_float64(b, s), d,
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
@@ -3616,9 +3616,9 @@ GEN_VEXT_VF(vfwnmsac_vf_w, 8)
#define OP_UU_W uint32_t, uint32_t, uint32_t
#define OP_UU_D uint64_t, uint64_t, uint64_t
-#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
+#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
*((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \
@@ -3626,7 +3626,7 @@ static void do_##NAME(void *vd, void *vs2, int i, \
#define GEN_VEXT_V_ENV(NAME, ESZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
+ CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
@@ -3703,9 +3703,9 @@ static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size)
}
int idx = ((exp & 1) << (precision - 1)) |
- (frac >> (frac_size - precision + 1));
+ (frac >> (frac_size - precision + 1));
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
- (frac_size - precision);
+ (frac_size - precision);
uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2;
uint64_t val = 0;
@@ -3727,9 +3727,9 @@ static float16 frsqrt7_h(float16 f, float_status *s)
* frsqrt7(-subnormal) = canonical NaN
*/
if (float16_is_signaling_nan(f, s) ||
- (float16_is_infinity(f) && sign) ||
- (float16_is_normal(f) && sign) ||
- (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
+ (float16_is_infinity(f) && sign) ||
+ (float16_is_normal(f) && sign) ||
+ (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float16_default_nan(s);
}
@@ -3767,9 +3767,9 @@ static float32 frsqrt7_s(float32 f, float_status *s)
* frsqrt7(-subnormal) = canonical NaN
*/
if (float32_is_signaling_nan(f, s) ||
- (float32_is_infinity(f) && sign) ||
- (float32_is_normal(f) && sign) ||
- (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
+ (float32_is_infinity(f) && sign) ||
+ (float32_is_normal(f) && sign) ||
+ (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float32_default_nan(s);
}
@@ -3807,9 +3807,9 @@ static float64 frsqrt7_d(float64 f, float_status *s)
* frsqrt7(-subnormal) = canonical NaN
*/
if (float64_is_signaling_nan(f, s) ||
- (float64_is_infinity(f) && sign) ||
- (float64_is_normal(f) && sign) ||
- (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
+ (float64_is_infinity(f) && sign) ||
+ (float64_is_normal(f) && sign) ||
+ (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float64_default_nan(s);
}
@@ -3897,18 +3897,18 @@ static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
((s->float_rounding_mode == float_round_up) && sign)) {
/* Return greatest/negative finite value. */
return (sign << (exp_size + frac_size)) |
- (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
+ (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
} else {
/* Return +-inf. */
return (sign << (exp_size + frac_size)) |
- MAKE_64BIT_MASK(frac_size, exp_size);
+ MAKE_64BIT_MASK(frac_size, exp_size);
}
}
}
int idx = frac >> (frac_size - precision);
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
- (frac_size - precision);
+ (frac_size - precision);
uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
if (out_exp == 0 || out_exp == UINT64_MAX) {
@@ -4422,8 +4422,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- *((ETYPE *)vd + H(i)) \
- = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
+ *((ETYPE *)vd + H(i)) = \
+ (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
env->vstart = 0; \
/* set tail elements to 1s */ \
@@ -4564,7 +4564,8 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
/* Vector Single-Width Integer Reduction Instructions */
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
@@ -5013,7 +5014,8 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
@@ -5061,7 +5063,8 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f2e3d38515..8e43bfc07c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -238,8 +238,8 @@ static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew)
{
int8_t emul = eew - s->sew + s->lmul;
return (emul >= -3 && emul <= 3) &&
- require_align(vd, emul) &&
- require_nf(vd, nf, emul);
+ require_align(vd, emul) &&
+ require_nf(vd, nf, emul);
}
/*
@@ -315,7 +315,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
int8_t seg_vd;
int8_t emul = eew - s->sew + s->lmul;
bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
- require_vm(vm, vd);
+ require_vm(vm, vd);
/* Each segment register group has to follow overlap rules. */
for (int i = 0; i < nf; ++i) {
@@ -345,8 +345,8 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
{
return require_vm(vm, vd) &&
- require_align(vd, s->lmul) &&
- require_align(vs, s->lmul);
+ require_align(vd, s->lmul) &&
+ require_align(vs, s->lmul);
}
/*
@@ -365,7 +365,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
return vext_check_ss(s, vd, vs2, vm) &&
- require_align(vs1, s->lmul);
+ require_align(vs1, s->lmul);
}
static bool vext_check_ms(DisasContext *s, int vd, int vs)
@@ -396,7 +396,7 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs)
static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
{
bool ret = vext_check_ms(s, vd, vs2) &&
- require_align(vs1, s->lmul);
+ require_align(vs1, s->lmul);
if (vd != vs1) {
ret &= require_noover(vd, 0, vs1, s->lmul);
}
@@ -460,14 +460,14 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
{
return vext_wide_check_common(s, vd, vm) &&
- require_align(vs, s->lmul) &&
- require_noover(vd, s->lmul + 1, vs, s->lmul);
+ require_align(vs, s->lmul) &&
+ require_noover(vd, s->lmul + 1, vs, s->lmul);
}
static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
{
return vext_wide_check_common(s, vd, vm) &&
- require_align(vs, s->lmul + 1);
+ require_align(vs, s->lmul + 1);
}
/*
@@ -485,8 +485,8 @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
return vext_check_ds(s, vd, vs2, vm) &&
- require_align(vs1, s->lmul) &&
- require_noover(vd, s->lmul + 1, vs1, s->lmul);
+ require_align(vs1, s->lmul) &&
+ require_noover(vd, s->lmul + 1, vs1, s->lmul);
}
/*
@@ -507,7 +507,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
return vext_check_ds(s, vd, vs1, vm) &&
- require_align(vs2, s->lmul + 1);
+ require_align(vs2, s->lmul + 1);
}
static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
@@ -535,7 +535,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
return vext_check_sd(s, vd, vs2, vm) &&
- require_align(vs1, s->lmul);
+ require_align(vs1, s->lmul);
}
/*
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 30/89] target/riscv: Fix format for comments
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (28 preceding siblings ...)
2023-05-05 1:01 ` [PULL 29/89] target/riscv: Fix format for indentation Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 31/89] target/riscv: Fix lines with over 80 characters Alistair Francis
` (60 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
LIU Zhiwei, Alistair Francis, Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Fix formats for multi-lines comments.
Add spaces around single line comments(after "/*" and before "*/").
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 26 ++++----
target/riscv/cpu_bits.h | 2 +-
target/riscv/sbi_ecall_interface.h | 8 +--
target/riscv/arch_dump.c | 3 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 57 +++++++++++------
target/riscv/csr.c | 6 +-
target/riscv/pmp.c | 41 +++++++------
target/riscv/translate.c | 20 +++---
target/riscv/vector_helper.c | 82 +++++++++++++++----------
target/riscv/insn_trans/trans_rvv.c.inc | 8 ++-
11 files changed, 151 insertions(+), 104 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 995192757a..5018a3b1b2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -124,7 +124,7 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
typedef struct PMUCTRState {
/* Current value of a counter */
target_ulong mhpmcounter_val;
- /* Current value of a counter in RV32*/
+ /* Current value of a counter in RV32 */
target_ulong mhpmcounterh_val;
/* Snapshot values of counter */
target_ulong mhpmcounter_prev;
@@ -280,8 +280,10 @@ struct CPUArchState {
target_ulong satp_hs;
uint64_t mstatus_hs;
- /* Signals whether the current exception occurred with two-stage address
- translation active. */
+ /*
+ * Signals whether the current exception occurred with two-stage address
+ * translation active.
+ */
bool two_stage_lookup;
/*
* Signals whether the current exception occurred while doing two-stage
@@ -297,10 +299,10 @@ struct CPUArchState {
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
- /* PMU event selector configured values. First three are unused*/
+ /* PMU event selector configured values. First three are unused */
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
- /* PMU event selector configured values for RV32*/
+ /* PMU event selector configured values for RV32 */
target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
target_ulong sscratch;
@@ -389,7 +391,7 @@ struct CPUArchState {
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
-/**
+/*
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
@@ -397,9 +399,9 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
* A RISCV CPU model.
*/
struct RISCVCPUClass {
- /*< private >*/
+ /* < private > */
CPUClass parent_class;
- /*< public >*/
+ /* < public > */
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
@@ -530,16 +532,16 @@ struct RISCVCPUConfig {
typedef struct RISCVCPUConfig RISCVCPUConfig;
-/**
+/*
* RISCVCPU:
* @env: #CPURISCVState
*
* A RISCV CPU.
*/
struct ArchCPU {
- /*< private >*/
+ /* < private > */
CPUState parent_obj;
- /*< public >*/
+ /* < public > */
CPUNegativeOffsetState neg;
CPURISCVState env;
@@ -813,7 +815,7 @@ enum {
CSR_TABLE_SIZE = 0x1000
};
-/**
+/*
* The event id are encoded based on the encoding specified in the
* SBI specification v0.3
*/
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 190e517862..101702cb4a 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -731,7 +731,7 @@ typedef enum RISCVException {
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
-/* General PointerMasking CSR bits*/
+/* General PointerMasking CSR bits */
#define PM_ENABLE 0x00000001ULL
#define PM_CURRENT 0x00000002ULL
#define PM_INSN 0x00000004ULL
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index 77574ed4cb..43899d08f6 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -28,7 +28,7 @@
#define SBI_EXT_RFENCE 0x52464E43
#define SBI_EXT_HSM 0x48534D
-/* SBI function IDs for BASE extension*/
+/* SBI function IDs for BASE extension */
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
#define SBI_EXT_BASE_GET_IMP_ID 0x1
#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
@@ -37,13 +37,13 @@
#define SBI_EXT_BASE_GET_MARCHID 0x5
#define SBI_EXT_BASE_GET_MIMPID 0x6
-/* SBI function IDs for TIME extension*/
+/* SBI function IDs for TIME extension */
#define SBI_EXT_TIME_SET_TIMER 0x0
-/* SBI function IDs for IPI extension*/
+/* SBI function IDs for IPI extension */
#define SBI_EXT_IPI_SEND_IPI 0x0
-/* SBI function IDs for RFENCE extension*/
+/* SBI function IDs for RFENCE extension */
#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
index 573587810e..434c8a3dbb 100644
--- a/target/riscv/arch_dump.c
+++ b/target/riscv/arch_dump.c
@@ -1,4 +1,5 @@
-/* Support for writing ELF notes for RISC-V architectures
+/*
+ * Support for writing ELF notes for RISC-V architectures
*
* Copyright (C) 2021 Huawei Technologies Co., Ltd
*
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8ed8601399..2e45b1f076 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -56,7 +56,7 @@ struct isa_ext_data {
#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
-/**
+/*
* Here are the ordering rules of extension naming defined by RISC-V
* specification :
* 1. All extensions should be separated from other multi-letter extensions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8d2547a164..445ffe691a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -717,7 +717,8 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
return TRANSLATE_SUCCESS;
}
-/* get_physical_address - get the physical address for this virtual address
+/*
+ * get_physical_address - get the physical address for this virtual address
*
* Do a page table walk to obtain the physical address corresponding to a
* virtual address. Returns 0 if the translation was successful
@@ -745,9 +746,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool first_stage, bool two_stage,
bool is_debug)
{
- /* NOTE: the env->pc value visible here will not be
+ /*
+ * NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
- * (riscv_cpu_do_interrupt) is correct */
+ * (riscv_cpu_do_interrupt) is correct
+ */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
@@ -767,8 +770,10 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true;
}
- /* MPRV does not affect the virtual-machine load/store
- instructions, HLV, HLVX, and HSV. */
+ /*
+ * MPRV does not affect the virtual-machine load/store
+ * instructions, HLV, HLVX, and HSV.
+ */
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
@@ -778,8 +783,10 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
if (first_stage == false) {
- /* We are in stage 2 translation, this is similar to stage 1. */
- /* Stage 2 is always taken as U-mode */
+ /*
+ * We are in stage 2 translation, this is similar to stage 1.
+ * Stage 2 is always taken as U-mode
+ */
mode = PRV_U;
}
@@ -1007,8 +1014,10 @@ restart:
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
- /* MTTCG is not enabled on oversized TCG guests so
- * page table updates do not need to be atomic */
+ /*
+ * MTTCG is not enabled on oversized TCG guests so
+ * page table updates do not need to be atomic
+ */
*pte_pa = pte = updated_pte;
#else
target_ulong old_pte =
@@ -1020,14 +1029,18 @@ restart:
}
#endif
} else {
- /* misconfigured PTE in ROM (AD bits are not preset) or
- * PTE is in IO space and can't be updated atomically */
+ /*
+ * misconfigured PTE in ROM (AD bits are not preset) or
+ * PTE is in IO space and can't be updated atomically
+ */
return TRANSLATE_FAIL;
}
}
- /* for superpage mappings, make a fake leaf PTE for the TLB's
- benefit. */
+ /*
+ * for superpage mappings, make a fake leaf PTE for the TLB's
+ * benefit.
+ */
target_ulong vpn = addr >> PGSHIFT;
if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
@@ -1049,8 +1062,10 @@ restart:
if (pte & PTE_X) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
+ /*
+ * add write permission on stores or if the page is already dirty,
+ * so that we TLB miss on later writes to update the dirty bit
+ */
if ((pte & PTE_W) &&
(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
*prot |= PAGE_WRITE;
@@ -1235,8 +1250,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /* MPRV does not affect the virtual-machine load/store
- instructions, HLV, HLVX, and HSV. */
+ /*
+ * MPRV does not affect the virtual-machine load/store
+ * instructions, HLV, HLVX, and HSV.
+ */
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
@@ -1577,7 +1594,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool write_gva = false;
uint64_t s;
- /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
+ /*
+ * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
* so we mask off the MSB and separate into trap type and cause.
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
@@ -1754,7 +1772,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_set_mode(env, PRV_M);
}
- /* NOTE: it is not necessary to yield load reservations here. It is only
+ /*
+ * NOTE: it is not necessary to yield load reservations here. It is only
* necessary for an SC from "another hart" to cause a load reservation
* to be yielded. Refer to the memory consistency model section of the
* RISC-V ISA Specification.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 41e56012d5..76755ee128 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -189,7 +189,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
}
ctr_index = csrno - base_csrno;
if (!pmu_num || ctr_index >= pmu_num) {
- /* The PMU is not enabled or counter is out of range*/
+ /* The PMU is not enabled or counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -877,7 +877,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
counter.mhpmcounter_val;
if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
- /**
+ /*
* Counter should not increment if inhibit bit is set. We can't really
* stop the icount counting. Just return the counter value written by
* the supervisor to indicate that counter was not incremented.
@@ -891,7 +891,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
}
}
- /**
+ /*
* The kernel computes the perf delta by subtracting the current value from
* the value it initialized previously (ctr_val).
*/
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3943b0f2e3..6ab2ae81c7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -132,15 +132,15 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
{
/*
- aaaa...aaa0 8-byte NAPOT range
- aaaa...aa01 16-byte NAPOT range
- aaaa...a011 32-byte NAPOT range
- ...
- aa01...1111 2^XLEN-byte NAPOT range
- a011...1111 2^(XLEN+1)-byte NAPOT range
- 0111...1111 2^(XLEN+2)-byte NAPOT range
- 1111...1111 Reserved
- */
+ * aaaa...aaa0 8-byte NAPOT range
+ * aaaa...aa01 16-byte NAPOT range
+ * aaaa...a011 32-byte NAPOT range
+ * ...
+ * aa01...1111 2^XLEN-byte NAPOT range
+ * a011...1111 2^(XLEN+1)-byte NAPOT range
+ * 0111...1111 2^(XLEN+2)-byte NAPOT range
+ * 1111...1111 Reserved
+ */
a = (a << 2) | 0x3;
*sa = a & (a + 1);
*ea = a | (a + 1);
@@ -205,7 +205,8 @@ void pmp_update_rule_nums(CPURISCVState *env)
}
}
-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
+/*
+ * Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
* end address values.
* This function is called relatively infrequently whereas the check that
* an address is within a pmp rule is called often, so optimise that one
@@ -329,8 +330,10 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
pmp_size = size;
}
- /* 1.10 draft priv spec states there is an implicit order
- from low to high */
+ /*
+ * 1.10 draft priv spec states there is an implicit order
+ * from low to high
+ */
for (i = 0; i < MAX_RISCV_PMPS; i++) {
s = pmp_is_in_range(env, i, addr);
e = pmp_is_in_range(env, i, addr + pmp_size - 1);
@@ -609,13 +612,13 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
return TARGET_PAGE_SIZE;
} else {
/*
- * At this point we have a tlb_size that is the smallest possible size
- * That fits within a TARGET_PAGE_SIZE and the PMP region.
- *
- * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
- * This means the result isn't cached in the TLB and is only used for
- * a single translation.
- */
+ * At this point we have a tlb_size that is the smallest possible size
+ * That fits within a TARGET_PAGE_SIZE and the PMP region.
+ *
+ * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
+ * This means the result isn't cached in the TLB and is only used for
+ * a single translation.
+ */
return 1;
}
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3613aca28d..d0094922b6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -69,11 +69,13 @@ typedef struct DisasContext {
uint32_t mstatus_hs_fs;
uint32_t mstatus_hs_vs;
uint32_t mem_idx;
- /* Remember the rounding mode encoded in the previous fp instruction,
- which we have already installed into env->fp_status. Or -1 for
- no previous fp instruction. Note that we exit the TB when writing
- to any system register, which includes CSR_FRM, so we do not have
- to reset this known value. */
+ /*
+ * Remember the rounding mode encoded in the previous fp instruction,
+ * which we have already installed into env->fp_status. Or -1 for
+ * no previous fp instruction. Note that we exit the TB when writing
+ * to any system register, which includes CSR_FRM, so we do not have
+ * to reset this known value.
+ */
int frm;
RISCVMXL ol;
bool virt_inst_excp;
@@ -491,7 +493,7 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
}
}
-/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
+/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
{
if (!ctx->cfg_ptr->ext_zfinx) {
@@ -598,7 +600,8 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
}
#ifndef CONFIG_USER_ONLY
-/* The states of mstatus_fs are:
+/*
+ * The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
@@ -636,7 +639,8 @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
#ifndef CONFIG_USER_ONLY
-/* The states of mstatus_vs are:
+/*
+ * The states of mstatus_vs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6067b5cfc7..81ac85b7d5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -287,7 +287,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
}
/*
- *** stride: access vector element from strided memory
+ * stride: access vector element from strided memory
*/
static void
vext_ldst_stride(void *vd, void *v0, target_ulong base,
@@ -353,10 +353,10 @@ GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/*
- *** unit-stride: access elements stored contiguously in memory
+ * unit-stride: access elements stored contiguously in memory
*/
-/* unmasked unit-stride load and store operation*/
+/* unmasked unit-stride load and store operation */
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
@@ -429,7 +429,7 @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
/*
- *** unit stride mask load and store, EEW = 1
+ * unit stride mask load and store, EEW = 1
*/
void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc)
@@ -450,7 +450,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
}
/*
- *** index: access vector element from indexed memory
+ * index: access vector element from indexed memory
*/
typedef target_ulong vext_get_index_addr(target_ulong base,
uint32_t idx, void *vs2);
@@ -554,7 +554,7 @@ GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
- *** unit-stride fault-only-fisrt load instructions
+ * unit-stride fault-only-fisrt load instructions
*/
static inline void
vext_ldff(void *vd, void *v0, target_ulong base,
@@ -571,7 +571,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t vma = vext_vma(desc);
target_ulong addr, offset, remain;
- /* probe every access*/
+ /* probe every access */
for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -660,7 +660,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
/*
- *** load and store whole register instructions
+ * load and store whole register instructions
*/
static void
vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
@@ -733,7 +733,7 @@ GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
/*
- *** Vector Integer Arithmetic Instructions
+ * Vector Integer Arithmetic Instructions
*/
/* expand macro args before macro */
@@ -1149,8 +1149,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -1185,8 +1187,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -1392,8 +1396,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -1455,8 +1461,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -2075,7 +2083,7 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4)
GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8)
/*
- *** Vector Fixed-Point Arithmetic Instructions
+ * Vector Fixed-Point Arithmetic Instructions
*/
/* Vector Single-Width Saturating Add and Subtract */
@@ -2988,7 +2996,7 @@ GEN_VEXT_VX_RM(vnclipu_wx_h, 2)
GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
/*
- *** Vector Float Point Arithmetic Instructions
+ * Vector Float Point Arithmetic Instructions
*/
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
@@ -4171,8 +4179,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
DO_OP(s2, s1, &env->fp_status)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -4208,8 +4218,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -4472,7 +4484,9 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8)
#define WOP_UU_B uint16_t, uint8_t, uint8_t
#define WOP_UU_H uint32_t, uint16_t, uint16_t
#define WOP_UU_W uint64_t, uint32_t, uint32_t
-/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
+/*
+ * vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.
+ */
RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
@@ -4559,7 +4573,7 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
/*
- *** Vector Reduction Operations
+ * Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
@@ -4713,7 +4727,7 @@ GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16)
GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
/*
- *** Vector Mask Operations
+ * Vector Mask Operations
*/
/* Vector Mask-Register Logical Instructions */
#define GEN_VEXT_MASK_VV(NAME, OP) \
@@ -4733,10 +4747,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail- \
- * agnostic \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
*/ \
- /* set tail elements to 1s */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
@@ -4779,7 +4793,7 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env,
return cnt;
}
-/* vfirst find-first-set mask bit*/
+/* vfirst find-first-set mask bit */
target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
@@ -4844,8 +4858,10 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
env->vstart = 0;
- /* mask destination register are always tail-agnostic */
- /* set tail elements to 1s */
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */
if (vta_all_1s) {
for (; i < total_elems; i++) {
vext_set_elem_mask(vd, i, 1);
@@ -4937,7 +4953,7 @@ GEN_VEXT_VID_V(vid_v_w, uint32_t, H4)
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8)
/*
- *** Vector Permutation Instructions
+ * Vector Permutation Instructions
*/
/* Vector Slide Instructions */
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8e43bfc07c..ca3c4c1a3d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3136,9 +3136,11 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
return false;
}
-/* vmsbf.m set-before-first mask bit */
-/* vmsif.m set-includ-first mask bit */
-/* vmsof.m set-only-first mask bit */
+/*
+ * vmsbf.m set-before-first mask bit
+ * vmsif.m set-including-first mask bit
+ * vmsof.m set-only-first mask bit
+ */
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 31/89] target/riscv: Fix lines with over 80 characters
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (29 preceding siblings ...)
2023-05-05 1:01 ` [PULL 30/89] target/riscv: Fix format for comments Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests Alistair Francis
` (59 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei,
Alistair Francis, Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Fix lines with over 80 characters for both code and comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 +-
target/riscv/cpu.c | 3 +-
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c | 38 ++++++++++--------
target/riscv/debug.c | 11 +++---
target/riscv/gdbstub.c | 3 +-
target/riscv/pmp.c | 6 ++-
target/riscv/pmu.c | 3 +-
target/riscv/vector_helper.c | 76 ++++++++++++++++++++++++------------
9 files changed, 91 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5018a3b1b2..cbf3de2708 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -591,8 +591,8 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr);
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2e45b1f076..cb68916fce 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1700,7 +1700,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
-static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
+ int max_str_len)
{
char *old = *isa_str;
char *new = *isa_str;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 445ffe691a..2310c7905f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1121,7 +1121,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ RISCV_EXCP_STORE_PAGE_FAULT :
+ RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
}
break;
default:
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 76755ee128..e0b871f6dc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1137,7 +1137,8 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
SIP_LCOFIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
-static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
+ MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
const bool valid_vm_1_10_32[16] = {
@@ -1298,7 +1299,8 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
Int128 *val)
{
- *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
+ *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128,
+ env->mstatus));
return RISCV_EXCP_NONE;
}
@@ -2823,7 +2825,8 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
{
env->hstatus = val;
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
- qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+ qemu_log_mask(LOG_UNIMP,
+ "QEMU does not support mixed HSXLEN options.");
}
if (get_field(val, HSTATUS_VSBE) != 0) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
@@ -3490,9 +3493,9 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & MMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "MMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
/* for machine mode pm.current is hardwired to 1 */
wpri_val |= MMTE_M_PM_CURRENT;
@@ -3521,9 +3524,9 @@ static RISCVException write_smte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & SMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "SMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
/* if pm.current==0 we can't modify current PM CSRs */
@@ -3549,9 +3552,9 @@ static RISCVException write_umte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & UMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "UMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
if (check_pm_current_disabled(env, csrno)) {
@@ -3941,7 +3944,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
* Fall back to 64-bit version for now, if the 128-bit alternative isn't
* at all defined.
* Note, some CSRs don't need to extend to MXLEN (64 upper bits non
- * significant), for those, this fallback is correctly handling the accesses
+ * significant), for those, this fallback is correctly handling the
+ * accesses
*/
target_ulong old_value;
ret = riscv_csrrw_do64(env, csrno, &old_value,
@@ -4154,11 +4158,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
- NULL, read_sstatus_i128 },
- [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
- [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
+ NULL, read_sstatus_i128 },
+ [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
- write_scounteren },
+ write_scounteren },
/* Supervisor Trap Handling */
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1f7aed23c9..75ee1c4971 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
/* validate size encoding */
size = type2_breakpoint_size(env, ctrl);
if (access_size[size] == -1) {
- qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
- size);
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
+ "SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE2_SIZELO);
if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
/* validate size encoding */
size = extract32(ctrl, 16, 4);
if (access_size[size] == -1) {
- qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
- size);
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
+ "SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE6_SIZE);
}
@@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
int trigger_type;
switch (tdata_index) {
case TDATA1:
- trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
+ trigger_type = extract_trigger_type(env,
+ env->tdata1[env->trigger_cur]);
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
itrigger_get_adjust_count(env));
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 692bbb64f6..fa537aed74 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
if (env->misa_ext & RVV) {
int base_reg = cs->gdb_num_regs;
- gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+ riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 6ab2ae81c7..1f5aca42e8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -129,7 +129,8 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
}
}
-static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
+static void pmp_decode_napot(target_ulong a, target_ulong *sa,
+ target_ulong *ea)
{
/*
* aaaa...aaa0 8-byte NAPOT range
@@ -217,7 +218,8 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
pmp_update_rule_nums(env);
}
-static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
+static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
+ target_ulong addr)
{
int result = 0;
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 48ad60be2b..db06b3882f 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -419,7 +419,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
} else {
return -1;
}
- overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
+ overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ overflow_ns;
if (overflow_at > INT64_MAX) {
overflow_left += overflow_at - INT64_MAX;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 81ac85b7d5..f4d0438988 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -382,8 +382,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
}
/*
- * masked unit-stride load and store operation will be a special case of stride,
- * stride = NF * sizeof (MTYPE)
+ * masked unit-stride load and store operation will be a special case of
+ * stride, stride = NF * sizeof (MTYPE)
*/
#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
@@ -678,7 +678,8 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/* load/store rest of elements of current segment pointed by vstart */
for (pos = off; pos < max_elems; pos++, env->vstart++) {
target_ulong addr = base + ((pos + k * max_elems) << log2_esz);
- ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd,
+ ra);
}
k++;
}
@@ -1306,7 +1307,9 @@ GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf)
GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f)
GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
-/* generate the helpers for shift instructions with one vector and one scalar */
+/*
+ * generate the helpers for shift instructions with one vector and one scalar
+ */
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, \
@@ -2165,7 +2168,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
do_##NAME, ESZ); \
}
-static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a,
+ uint8_t b)
{
uint8_t res = a + b;
if (res < a) {
@@ -2309,7 +2313,8 @@ static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
return res;
}
-static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a,
+ int16_t b)
{
int16_t res = a + b;
if ((res ^ a) & (res ^ b) & INT16_MIN) {
@@ -2319,7 +2324,8 @@ static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
return res;
}
-static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int32_t res = a + b;
if ((res ^ a) & (res ^ b) & INT32_MIN) {
@@ -2329,7 +2335,8 @@ static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
return res;
}
-static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a + b;
if ((res ^ a) & (res ^ b) & INT64_MIN) {
@@ -2357,7 +2364,8 @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2)
GEN_VEXT_VX_RM(vsadd_vx_w, 4)
GEN_VEXT_VX_RM(vsadd_vx_d, 8)
-static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a,
+ uint8_t b)
{
uint8_t res = a - b;
if (res > a) {
@@ -2428,7 +2436,8 @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
return res;
}
-static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a,
+ int16_t b)
{
int16_t res = a - b;
if ((res ^ a) & (a ^ b) & INT16_MIN) {
@@ -2438,7 +2447,8 @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
return res;
}
-static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int32_t res = a - b;
if ((res ^ a) & (a ^ b) & INT32_MIN) {
@@ -2448,7 +2458,8 @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
return res;
}
-static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a - b;
if ((res ^ a) & (a ^ b) & INT64_MIN) {
@@ -2504,7 +2515,8 @@ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
return 0; /* round-down (truncate) */
}
-static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int64_t res = (int64_t)a + b;
uint8_t round = get_round(vxrm, res, 1);
@@ -2512,7 +2524,8 @@ static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
return (res >> 1) + round;
}
-static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a + b;
uint8_t round = get_round(vxrm, res, 1);
@@ -2577,7 +2590,8 @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2)
GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
-static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
@@ -2585,7 +2599,8 @@ static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
return (res >> 1) + round;
}
-static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
@@ -4498,7 +4513,9 @@ RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
-/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+/*
+ * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.
+ */
RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
@@ -4515,8 +4532,7 @@ GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
/*
- * vfwcvt.f.f.v vd, vs2, vm
- * Convert single-width float to double-width float.
+ * vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.
*/
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
{
@@ -4549,7 +4565,9 @@ GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1)
GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
-/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
+/*
+ * vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float.
+ */
RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2)
@@ -4699,14 +4717,20 @@ GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_number)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2,
+ float16_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4,
+ float32_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8,
+ float64_maximum_number)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2,
+ float16_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4,
+ float32_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
+ float64_minimum_number)
/* Vector Widening Floating-Point Add Instructions */
static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (30 preceding siblings ...)
2023-05-05 1:01 ` [PULL 31/89] target/riscv: Fix lines with over 80 characters Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Alistair Francis
` (58 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add signature and signature-granularity properties in spike to specify the target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_signature symbols
when loading elf of ACT tests. Then dump signature data in signature section just
before the ACT tests exit.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230405095720.75848-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/char/riscv_htif.h | 3 +++
hw/char/riscv_htif.c | 44 +++++++++++++++++++++++++++++++++++-
hw/riscv/spike.c | 13 +++++++++++
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index 5958c5b986..df493fdf6b 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -40,6 +40,9 @@ typedef struct HTIFState {
uint64_t pending_read;
} HTIFState;
+extern const char *sig_file;
+extern uint8_t line_size;
+
/* HTIF symbol callback */
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size);
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 098de50e35..37d3ccc76b 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -29,6 +29,8 @@
#include "chardev/char-fe.h"
#include "qemu/timer.h"
#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
+#include "sysemu/dma.h"
#define RISCV_DEBUG_HTIF 0
#define HTIF_DEBUG(fmt, ...) \
@@ -51,7 +53,10 @@
/* PK system call number */
#define PK_SYS_WRITE 64
-static uint64_t fromhost_addr, tohost_addr;
+const char *sig_file;
+uint8_t line_size = 16;
+
+static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size)
@@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
error_report("HTIF tohost must be 8 bytes");
exit(1);
}
+ } else if (strcmp("begin_signature", st_name) == 0) {
+ begin_sig_addr = st_value;
+ } else if (strcmp("end_signature", st_name) == 0) {
+ end_sig_addr = st_value;
}
}
@@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
if (payload & 0x1) {
/* exit code */
int exit_code = payload >> 1;
+
+ /*
+ * Dump signature data if sig_file is specified and
+ * begin/end_signature symbols exist.
+ */
+ if (sig_file && begin_sig_addr && end_sig_addr) {
+ uint64_t sig_len = end_sig_addr - begin_sig_addr;
+ char *sig_data = g_malloc(sig_len);
+ dma_memory_read(&address_space_memory, begin_sig_addr,
+ sig_data, sig_len, MEMTXATTRS_UNSPECIFIED);
+ FILE *signature = fopen(sig_file, "w");
+ if (signature == NULL) {
+ error_report("Unable to open %s with error %s",
+ sig_file, strerror(errno));
+ exit(1);
+ }
+
+ for (int i = 0; i < sig_len; i += line_size) {
+ for (int j = line_size; j > 0; j--) {
+ if (i + j <= sig_len) {
+ fprintf(signature, "%02x",
+ sig_data[i + j - 1] & 0xff);
+ } else {
+ fprintf(signature, "%02x", 0);
+ }
+ }
+ fprintf(signature, "\n");
+ }
+
+ fclose(signature);
+ g_free(sig_data);
+ }
+
exit(exit_code);
} else {
uint64_t syscall[8];
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index a584d5b3a2..2c5546560a 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -332,6 +332,11 @@ static void spike_board_init(MachineState *machine)
htif_custom_base);
}
+static void spike_set_signature(Object *obj, const char *val, Error **errp)
+{
+ sig_file = g_strdup(val);
+}
+
static void spike_machine_instance_init(Object *obj)
{
}
@@ -350,6 +355,14 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
mc->numa_mem_supported = true;
mc->default_ram_id = "riscv.spike.ram";
+ object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
+ object_class_property_set_description(oc, "signature",
+ "File to write ACT test signature");
+ object_class_property_add_uint8_ptr(oc, "signature-granularity",
+ &line_size, OBJ_PROP_FLAG_WRITE);
+ object_class_property_set_description(oc, "signature-granularity",
+ "Size of each line in ACT signature "
+ "file");
}
static const TypeInfo spike_machine_typeinfo = {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (31 preceding siblings ...)
2023-05-05 1:01 ` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Alistair Francis
` (57 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
properties updated. The same can't be said about env->misa_ext*, since
the user might enable/disable MISA extensions in the command line, and
env->misa_ext* won't caught these changes. The current solution is to
sync everything at the end of validate_set_extensions(), checking every
cpu->cfg.ext_N value to do a set_misa() in the end.
The last change we're making in the MISA cfg flags are in the G
extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise
we're not making any changes in MISA bits ever since realize() starts.
There's no reason to postpone misa_ext updates until the end of the
validation. Let's do it earlier, during realize(), in a new helper
called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it
again by updating env->misa_ext* directly.
This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to
use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA
extensions, which is our end goal here.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 94 +++++++++++++++++++++++++++-------------------
1 file changed, 56 insertions(+), 38 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cb68916fce..66de3bb33f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -811,12 +811,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
/*
* Check consistency between chosen extensions while setting
- * cpu->cfg accordingly, doing a set_misa() in the end.
+ * cpu->cfg accordingly.
*/
static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
- uint32_t ext = 0;
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
@@ -831,6 +830,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
+
+ env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
+ env->misa_ext_mask = env->misa_ext;
}
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
@@ -1022,39 +1024,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksh = true;
}
- if (cpu->cfg.ext_i) {
- ext |= RVI;
- }
- if (cpu->cfg.ext_e) {
- ext |= RVE;
- }
- if (cpu->cfg.ext_m) {
- ext |= RVM;
- }
- if (cpu->cfg.ext_a) {
- ext |= RVA;
- }
- if (cpu->cfg.ext_f) {
- ext |= RVF;
- }
- if (cpu->cfg.ext_d) {
- ext |= RVD;
- }
- if (cpu->cfg.ext_c) {
- ext |= RVC;
- }
- if (cpu->cfg.ext_s) {
- ext |= RVS;
- }
- if (cpu->cfg.ext_u) {
- ext |= RVU;
- }
- if (cpu->cfg.ext_h) {
- ext |= RVH;
- }
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_1_00_0;
- ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
"Vector extension VLEN must be power of 2");
@@ -1092,11 +1063,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
set_vext_version(env, vext_version);
}
- if (cpu->cfg.ext_j) {
- ext |= RVJ;
- }
-
- set_misa(env, env->misa_mxl, ext);
}
#ifndef CONFIG_USER_ONLY
@@ -1181,6 +1147,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
#endif
}
+static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
+{
+ uint32_t ext = 0;
+
+ if (riscv_cpu_cfg(env)->ext_i) {
+ ext |= RVI;
+ }
+ if (riscv_cpu_cfg(env)->ext_e) {
+ ext |= RVE;
+ }
+ if (riscv_cpu_cfg(env)->ext_m) {
+ ext |= RVM;
+ }
+ if (riscv_cpu_cfg(env)->ext_a) {
+ ext |= RVA;
+ }
+ if (riscv_cpu_cfg(env)->ext_f) {
+ ext |= RVF;
+ }
+ if (riscv_cpu_cfg(env)->ext_d) {
+ ext |= RVD;
+ }
+ if (riscv_cpu_cfg(env)->ext_c) {
+ ext |= RVC;
+ }
+ if (riscv_cpu_cfg(env)->ext_s) {
+ ext |= RVS;
+ }
+ if (riscv_cpu_cfg(env)->ext_u) {
+ ext |= RVU;
+ }
+ if (riscv_cpu_cfg(env)->ext_h) {
+ ext |= RVH;
+ }
+ if (riscv_cpu_cfg(env)->ext_v) {
+ ext |= RVV;
+ }
+ if (riscv_cpu_cfg(env)->ext_j) {
+ ext |= RVJ;
+ }
+
+ env->misa_ext = env->misa_ext_mask = ext;
+}
+
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -1216,6 +1226,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_priv_version(env, priv_version);
}
+ /*
+ * We can't be sure of whether we set defaults during cpu_init()
+ * or whether the user enabled/disabled some bits via cpu->cfg
+ * flags. Sync env->misa_ext with cpu->cfg now to allow us to
+ * use just env->misa_ext later.
+ */
+ riscv_cpu_sync_misa_cfg(env);
+
/* Force disable extensions if priv spec version does not match */
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[]
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (32 preceding siblings ...)
2023-05-05 1:01 ` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Alistair Francis
` (56 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing it from
isa_edata_arr[].
We're also erroring it out instead of disabling, making the cpu_init()
function responsible for running an adequate priv spec for the MISA
extensions it wants to use.
Note that the RVV verification is being ignored since we're always have
at least PRIV_VERSION_1_10_0.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66de3bb33f..ed8f36c649 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -72,10 +72,11 @@ struct isa_ext_data {
* 4. Non-standard extensions (starts with 'X') must be listed after all
* standard extensions. They must be separated from other multi-letter
* extensions by an underscore.
+ *
+ * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
+ * instead.
*/
static const struct isa_ext_data isa_edata_arr[] = {
- ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
- ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
@@ -1191,6 +1192,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
env->misa_ext = env->misa_ext_mask = ext;
}
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
+{
+ if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
+ error_setg(errp, "H extension requires priv spec 1.12.0");
+ return;
+ }
+}
+
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -1234,6 +1243,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
*/
riscv_cpu_sync_misa_cfg(env);
+ riscv_cpu_validate_misa_priv(env, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* Force disable extensions if priv spec version does not match */
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (33 preceding siblings ...)
2023-05-05 1:01 ` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties() Alistair Francis
` (55 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
redundant 'multi_letter' field from isa_ext_data.
Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 132 ++++++++++++++++++++++-----------------------
1 file changed, 65 insertions(+), 67 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ed8f36c649..fbf612292a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -48,13 +48,12 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
const char *name;
- bool multi_letter;
int min_version;
int ext_enable_offset;
};
-#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
- {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
+ {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
/*
* Here are the ordering rules of extension naming defined by RISC-V
@@ -77,68 +76,68 @@ struct isa_ext_data {
* instead.
*/
static const struct isa_ext_data isa_edata_arr[] = {
- ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
- ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
- ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
- ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
- ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
- ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
- ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
- ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
- ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
- ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
- ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
- ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
- ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
- ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
- ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
- ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce),
- ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
- ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
- ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
- ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
- ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
- ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
- ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
- ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
- ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
- ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
- ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
- ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
- ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
- ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
- ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
- ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
- ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
- ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
- ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
- ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f),
- ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f),
- ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d),
- ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
- ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
- ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
- ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
- ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
- ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
- ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
- ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
- ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
- ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
- ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
- ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
- ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
- ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
- ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
- ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
- ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
- ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
- ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
- ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
- ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
- ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
- ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
- ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
+ ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
+ ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
+ ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
+ ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
+ ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
+ ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
+ ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
+ ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
+ ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
+ ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
+ ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
+ ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
+ ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
+ ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
+ ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
+ ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
+ ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
+ ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
+ ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
+ ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
+ ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
+ ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
+ ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
+ ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
+ ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
+ ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
+ ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
+ ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
+ ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
+ ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
+ ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
+ ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
+ ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
+ ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+ ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+ ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+ ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
+ ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+ ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
+ ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+ ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
+ ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
+ ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
+ ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
+ ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
+ ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
+ ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
+ ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
+ ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
+ ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+ ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
+ ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
+ ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
+ ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
+ ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
+ ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
+ ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
+ ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
static bool isa_ext_is_enabled(RISCVCPU *cpu,
@@ -1741,8 +1740,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int i;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_edata_arr[i].multi_letter &&
- isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
g_free(old);
old = new;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (34 preceding siblings ...)
2023-05-05 1:01 ` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Alistair Francis
` (54 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
in the command line. User settings are reflected in the cpu->cfg object
for later use. These properties are used in the target/riscv/cpu.c code,
most notably in riscv_cpu_validate_set_extensions(), where most of our
realize time validations are made.
And then there's env->misa_ext, the field where the MISA extensions are
set, that is read everywhere else. We need to keep env->misa_ext updated
with cpu->cfg settings, since our validations rely on it, forcing us to
make register_cpu_props() write cpu->cfg.ext_N flags to cover for named
CPUs that aren't used named properties but also needs to go through the
same validation steps. Failing to so will make those name CPUs fail
validation (see c66ffcd5358b for more info). Not only that, but we also
need to sync env->misa_ext with cpu->cfg again during realize() time to
catch any change the user might have done, since the rest of the code
relies on that.
Making cpu->cfg.ext_N and env->misa_ext reflect each other is not
needed. What we want is a way for users to enable/disable MISA extensions,
and there's nothing stopping us from letting the user write env->misa_ext
directly. Here are the artifacts that will enable us to do that:
- RISCVCPUMisaExtConfig will declare each MISA property;
- cpu_set_misa_ext_cfg() is the setter for each property. We'll write
env->misa_ext and env->misa_ext_mask with the appropriate misa_bit;
cutting off cpu->cfg.ext_N from the logic;
- cpu_get_misa_ext_cfg() is a getter that will retrieve the current val
of the property based on env->misa_ext;
- riscv_cpu_add_misa_properties() will be called in register_cpu_props()
to init all MISA properties from the misa_ext_cfgs[] array.
With this infrastructure we'll start to get rid of each cpu->cfg.ext_N
attribute in the next patches.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fbf612292a..3b234a03d0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1453,6 +1453,69 @@ static void riscv_cpu_init(Object *obj)
#endif /* CONFIG_USER_ONLY */
}
+typedef struct RISCVCPUMisaExtConfig {
+ const char *name;
+ const char *description;
+ target_ulong misa_bit;
+ bool enabled;
+} RISCVCPUMisaExtConfig;
+
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ if (value) {
+ env->misa_ext |= misa_bit;
+ env->misa_ext_mask |= misa_bit;
+ } else {
+ env->misa_ext &= ~misa_bit;
+ env->misa_ext_mask &= ~misa_bit;
+ }
+}
+
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ value = env->misa_ext & misa_bit;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
+
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+
+ object_property_add(cpu_obj, misa_cfg->name, "bool",
+ cpu_get_misa_ext_cfg,
+ cpu_set_misa_ext_cfg,
+ NULL, (void *)misa_cfg);
+ object_property_set_description(cpu_obj, misa_cfg->name,
+ misa_cfg->description);
+ object_property_set_bool(cpu_obj, misa_cfg->name,
+ misa_cfg->enabled, NULL);
+ }
+}
+
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
@@ -1599,6 +1662,8 @@ static void register_cpu_props(Object *obj)
return;
}
+ riscv_cpu_add_misa_properties(obj);
+
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
qdev_property_add_static(dev, prop);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 37/89] target/riscv: remove cpu->cfg.ext_a
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (35 preceding siblings ...)
2023-05-05 1:01 ` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties() Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Alistair Francis
` (53 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 16 ++++++++--------
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cbf3de2708..1d1a17d85b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -426,7 +426,6 @@ struct RISCVCPUConfig {
bool ext_e;
bool ext_g;
bool ext_m;
- bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3b234a03d0..3770fd4f6f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
- cpu->cfg.ext_a && cpu->cfg.ext_f &&
- cpu->cfg.ext_d &&
+ riscv_has_ext(env, RVA) &&
+ cpu->cfg.ext_f && cpu->cfg.ext_d &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
- cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
@@ -869,7 +868,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
+ if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
@@ -1160,7 +1159,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_m) {
ext |= RVM;
}
- if (riscv_cpu_cfg(env)->ext_a) {
+ if (riscv_has_ext(env, RVA)) {
ext |= RVA;
}
if (riscv_cpu_cfg(env)->ext_f) {
@@ -1496,7 +1495,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
visit_type_bool(v, name, &value, errp);
}
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+ {.name = "a", .description = "Atomic instructions",
+ .misa_bit = RVA, .enabled = true},
+};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
@@ -1522,7 +1524,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
- DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
@@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
- cpu->cfg.ext_a = misa_ext & RVA;
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 38/89] target/riscv: remove cpu->cfg.ext_c
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (36 preceding siblings ...)
2023-05-05 1:01 ` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Alistair Francis
` (52 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 9 ++++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1d1a17d85b..9a3847329c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -428,7 +428,6 @@ struct RISCVCPUConfig {
bool ext_m;
bool ext_f;
bool ext_d;
- bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3770fd4f6f..2e00b8f20a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
- cpu->cfg.ext_c = true;
cpu->cfg.ext_u = true;
cpu->cfg.ext_s = true;
cpu->cfg.ext_icsr = true;
@@ -957,7 +956,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
- if (cpu->cfg.ext_c) {
+ if (riscv_has_ext(env, RVC)) {
cpu->cfg.ext_zca = true;
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
@@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_d) {
ext |= RVD;
}
- if (riscv_cpu_cfg(env)->ext_c) {
+ if (riscv_has_ext(env, RVC)) {
ext |= RVC;
}
if (riscv_cpu_cfg(env)->ext_s) {
@@ -1498,6 +1497,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
{.name = "a", .description = "Atomic instructions",
.misa_bit = RVA, .enabled = true},
+ {.name = "c", .description = "Compressed instructions",
+ .misa_bit = RVC, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
- DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1649,7 +1649,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_c = misa_ext & RVC;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 39/89] target/riscv: remove cpu->cfg.ext_d
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (37 preceding siblings ...)
2023-05-05 1:01 ` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f Alistair Francis
` (51 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 17 ++++++++---------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9a3847329c..fba5e9a33c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -427,7 +427,6 @@ struct RISCVCPUConfig {
bool ext_g;
bool ext_m;
bool ext_f;
- bool ext_d;
bool ext_s;
bool ext_u;
bool ext_h;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2e00b8f20a..5bb03e2ee5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) &&
- cpu->cfg.ext_f && cpu->cfg.ext_d &&
+ cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_f = true;
- cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -881,7 +880,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
+ if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
error_setg(errp, "D extension requires F extension");
return;
}
@@ -901,7 +900,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zve32f = true;
}
- if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
+ if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
@@ -961,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
}
- if (cpu->cfg.ext_d) {
+ if (riscv_has_ext(env, RVD)) {
cpu->cfg.ext_zcd = true;
}
}
@@ -976,7 +975,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
+ if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
error_setg(errp, "Zcd extension requires D extension");
return;
}
@@ -1164,7 +1163,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_f) {
ext |= RVF;
}
- if (riscv_cpu_cfg(env)->ext_d) {
+ if (riscv_has_ext(env, RVD)) {
ext |= RVD;
}
if (riscv_has_ext(env, RVC)) {
@@ -1499,6 +1498,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVA, .enabled = true},
{.name = "c", .description = "Compressed instructions",
.misa_bit = RVC, .enabled = true},
+ {.name = "d", .description = "Double-precision float point",
+ .misa_bit = RVD, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
- DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_f = misa_ext & RVF;
- cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 40/89] target/riscv: remove cpu->cfg.ext_f
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (38 preceding siblings ...)
2023-05-05 1:01 ` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Alistair Francis
` (50 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "f" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
replaced with riscv_has_ext(env, RVF).
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 26 +++++++++++++-------------
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fba5e9a33c..e5680b0709 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -426,7 +426,6 @@ struct RISCVCPUConfig {
bool ext_e;
bool ext_g;
bool ext_m;
- bool ext_f;
bool ext_s;
bool ext_u;
bool ext_h;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5bb03e2ee5..715cbca1b3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -819,12 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) &&
- cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
+ riscv_has_ext(env, RVF) &&
+ riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
- cpu->cfg.ext_f = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -861,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+ if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
}
@@ -875,12 +875,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zfhmin = true;
}
- if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
- if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
+ if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
error_setg(errp, "D extension requires F extension");
return;
}
@@ -905,7 +905,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
@@ -938,7 +938,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zfinx extension requires Zicsr");
return;
}
- if (cpu->cfg.ext_f) {
+ if (riscv_has_ext(env, RVF)) {
error_setg(errp,
"Zfinx cannot be supported together with F extension");
return;
@@ -950,14 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zcb = true;
cpu->cfg.ext_zcmp = true;
cpu->cfg.ext_zcmt = true;
- if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
}
}
if (riscv_has_ext(env, RVC)) {
cpu->cfg.ext_zca = true;
- if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
}
if (riscv_has_ext(env, RVD)) {
@@ -970,7 +970,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
+ if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension requires F extension");
return;
}
@@ -1160,7 +1160,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVA)) {
ext |= RVA;
}
- if (riscv_cpu_cfg(env)->ext_f) {
+ if (riscv_has_ext(env, RVF)) {
ext |= RVF;
}
if (riscv_has_ext(env, RVD)) {
@@ -1500,6 +1500,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVC, .enabled = true},
{.name = "d", .description = "Double-precision float point",
.misa_bit = RVD, .enabled = true},
+ {.name = "f", .description = "Single-precision float point",
+ .misa_bit = RVF, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1526,7 +1528,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
- DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1646,7 +1647,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
- cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 41/89] target/riscv: remove cpu->cfg.ext_i
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (39 preceding siblings ...)
2023-05-05 1:01 ` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Alistair Francis
` (49 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "i" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
replaced with riscv_has_ext(env, RVI).
Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 15 +++++++--------
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e5680b0709..479b654d54 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -422,7 +422,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
- bool ext_i;
bool ext_e;
bool ext_g;
bool ext_m;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 715cbca1b3..f082748569 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -817,13 +817,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+ if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -832,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
env->misa_ext_mask = env->misa_ext;
}
- if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+ if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
- if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
error_setg(errp,
"Either I or E extension must be set");
return;
@@ -850,7 +849,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+ if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
@@ -1148,7 +1147,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
{
uint32_t ext = 0;
- if (riscv_cpu_cfg(env)->ext_i) {
+ if (riscv_has_ext(env, RVI)) {
ext |= RVI;
}
if (riscv_cpu_cfg(env)->ext_e) {
@@ -1502,6 +1501,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVD, .enabled = true},
{.name = "f", .description = "Single-precision float point",
.misa_bit = RVF, .enabled = true},
+ {.name = "i", .description = "Base integer instruction set",
+ .misa_bit = RVI, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1524,7 +1525,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
- DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
@@ -1644,7 +1644,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 42/89] target/riscv: remove cpu->cfg.ext_e
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (40 preceding siblings ...)
2023-05-05 1:01 ` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Alistair Francis
` (48 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 10 +++++-----
target/riscv/insn_trans/trans_rvzce.c.inc | 2 +-
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 479b654d54..2b42de60b1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -422,7 +422,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
- bool ext_e;
bool ext_g;
bool ext_m;
bool ext_s;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f082748569..33db4fa4b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -831,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
env->misa_ext_mask = env->misa_ext;
}
- if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
+ if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
- if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
+ if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
error_setg(errp,
"Either I or E extension must be set");
return;
@@ -1150,7 +1150,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVI)) {
ext |= RVI;
}
- if (riscv_cpu_cfg(env)->ext_e) {
+ if (riscv_has_ext(env, RVE)) {
ext |= RVE;
}
if (riscv_cpu_cfg(env)->ext_m) {
@@ -1503,6 +1503,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVF, .enabled = true},
{.name = "i", .description = "Base integer instruction set",
.misa_bit = RVI, .enabled = true},
+ {.name = "e", .description = "Base integer instruction set (embedded)",
+ .misa_bit = RVE, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1525,7 +1527,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
- DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
@@ -1644,7 +1645,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index d75acbc4a6..a727169a4b 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -117,7 +117,7 @@ static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
{
uint32_t reg_bitmap = 0;
- if (ctx->cfg_ptr->ext_e && rlist > 6) {
+ if (has_ext(ctx, RVE) && rlist > 6) {
return 0;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 43/89] target/riscv: remove cpu->cfg.ext_m
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (41 preceding siblings ...)
2023-05-05 1:01 ` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Alistair Francis
` (47 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 10 +++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2b42de60b1..71540a33ec 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_m;
bool ext_s;
bool ext_u;
bool ext_h;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 33db4fa4b2..24640450c7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
+ if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
+ riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_m = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVE)) {
ext |= RVE;
}
- if (riscv_cpu_cfg(env)->ext_m) {
+ if (riscv_has_ext(env, RVM)) {
ext |= RVM;
}
if (riscv_has_ext(env, RVA)) {
@@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVI, .enabled = true},
{.name = "e", .description = "Base integer instruction set (embedded)",
.misa_bit = RVE, .enabled = false},
+ {.name = "m", .description = "Integer multiplication and division",
+ .misa_bit = RVM, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 44/89] target/riscv: remove cpu->cfg.ext_s
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (42 preceding siblings ...)
2023-05-05 1:01 ` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Alistair Francis
` (46 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "s" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
replaced with riscv_has_ext(env, RVS).
Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 11 +++++------
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 71540a33ec..8b8e541e5f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 24640450c7..cded82ac7a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -408,7 +408,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.ext_g = true;
cpu->cfg.ext_u = true;
- cpu->cfg.ext_s = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+ if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
@@ -855,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
+ if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
@@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVC)) {
ext |= RVC;
}
- if (riscv_cpu_cfg(env)->ext_s) {
+ if (riscv_has_ext(env, RVS)) {
ext |= RVS;
}
if (riscv_cpu_cfg(env)->ext_u) {
@@ -1507,6 +1506,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVE, .enabled = false},
{.name = "m", .description = "Integer multiplication and division",
.misa_bit = RVM, .enabled = true},
+ {.name = "s", .description = "Supervisor-level instructions",
+ .misa_bit = RVS, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1530,7 +1531,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
@@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 45/89] target/riscv: remove cpu->cfg.ext_u
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (43 preceding siblings ...)
2023-05-05 1:01 ` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Alistair Francis
` (45 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 9 ++++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b8e541e5f..486061589e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_u;
bool ext_h;
bool ext_j;
bool ext_v;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cded82ac7a..9565495839 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
- cpu->cfg.ext_u = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@@ -842,7 +841,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
+ if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
@@ -1170,7 +1169,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVS)) {
ext |= RVS;
}
- if (riscv_cpu_cfg(env)->ext_u) {
+ if (riscv_has_ext(env, RVU)) {
ext |= RVU;
}
if (riscv_cpu_cfg(env)->ext_h) {
@@ -1508,6 +1507,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVM, .enabled = true},
{.name = "s", .description = "Supervisor-level instructions",
.misa_bit = RVS, .enabled = true},
+ {.name = "u", .description = "User-level instructions",
+ .misa_bit = RVU, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1531,7 +1532,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
@@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 46/89] target/riscv: remove cpu->cfg.ext_h
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (44 preceding siblings ...)
2023-05-05 1:01 ` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:01 ` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Alistair Francis
` (44 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 10 +++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 486061589e..823be82239 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_h;
bool ext_j;
bool ext_v;
bool ext_zba;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9565495839..6291224905 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -847,13 +847,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
}
- if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
@@ -1172,7 +1172,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVU)) {
ext |= RVU;
}
- if (riscv_cpu_cfg(env)->ext_h) {
+ if (riscv_has_ext(env, RVH)) {
ext |= RVH;
}
if (riscv_cpu_cfg(env)->ext_v) {
@@ -1509,6 +1509,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVS, .enabled = true},
{.name = "u", .description = "User-level instructions",
.misa_bit = RVU, .enabled = true},
+ {.name = "h", .description = "Hypervisor",
+ .misa_bit = RVH, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1533,7 +1535,6 @@ static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
@@ -1647,7 +1648,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
/*
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 47/89] target/riscv: remove cpu->cfg.ext_j
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (45 preceding siblings ...)
2023-05-05 1:01 ` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Alistair Francis
@ 2023-05-05 1:01 ` Alistair Francis
2023-05-05 1:02 ` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Alistair Francis
` (43 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:01 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 6 +++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 823be82239..1aff93ba91 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6291224905..3bdd6875a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_v) {
ext |= RVV;
}
- if (riscv_cpu_cfg(env)->ext_j) {
+ if (riscv_has_ext(env, RVJ)) {
ext |= RVJ;
}
@@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVU, .enabled = true},
{.name = "h", .description = "Hypervisor",
.misa_bit = RVH, .enabled = true},
+ {.name = "x-j", .description = "Dynamic translated languages",
+ .misa_bit = RVJ, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
@@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_j = misa_ext & RVJ;
/*
* We don't want to set the default riscv_cpu_extensions
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 48/89] target/riscv: remove cpu->cfg.ext_v
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (46 preceding siblings ...)
2023-05-05 1:01 ` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Alistair Francis
` (42 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 12 +++++-------
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1aff93ba91..e011cf6ca4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3bdd6875a8..13ff37250e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -883,7 +883,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
/* The V vector extension depends on the Zve64d extension */
- if (cpu->cfg.ext_v) {
+ if (riscv_has_ext(env, RVV)) {
cpu->cfg.ext_zve64d = true;
}
@@ -1018,7 +1018,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksh = true;
}
- if (cpu->cfg.ext_v) {
+ if (riscv_has_ext(env, RVV)) {
int vext_version = VEXT_VERSION_1_00_0;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
@@ -1175,7 +1175,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVH)) {
ext |= RVH;
}
- if (riscv_cpu_cfg(env)->ext_v) {
+ if (riscv_has_ext(env, RVV)) {
ext |= RVV;
}
if (riscv_has_ext(env, RVJ)) {
@@ -1513,6 +1513,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVH, .enabled = true},
{.name = "x-j", .description = "Dynamic translated languages",
.misa_bit = RVJ, .enabled = false},
+ {.name = "v", .description = "Vector operations",
+ .misa_bit = RVV, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1536,7 +1538,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
@@ -1638,7 +1639,6 @@ static Property riscv_cpu_extensions[] = {
static void register_cpu_props(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
DeviceState *dev = DEVICE(obj);
@@ -1648,8 +1648,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_v = misa_ext & RVV;
-
/*
* We don't want to set the default riscv_cpu_extensions
* in this case.
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (47 preceding siblings ...)
2023-05-05 1:02 ` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Alistair Francis
` (41 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an existing MISA bit
(cfg.ext_g will be handled shortly). The function is now a no-op, simply
copying the existing values of misa_ext* back to misa_ext*.
Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 52 ----------------------------------------------
1 file changed, 52 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13ff37250e..1ecb82bb5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1141,50 +1141,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
#endif
}
-static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
-{
- uint32_t ext = 0;
-
- if (riscv_has_ext(env, RVI)) {
- ext |= RVI;
- }
- if (riscv_has_ext(env, RVE)) {
- ext |= RVE;
- }
- if (riscv_has_ext(env, RVM)) {
- ext |= RVM;
- }
- if (riscv_has_ext(env, RVA)) {
- ext |= RVA;
- }
- if (riscv_has_ext(env, RVF)) {
- ext |= RVF;
- }
- if (riscv_has_ext(env, RVD)) {
- ext |= RVD;
- }
- if (riscv_has_ext(env, RVC)) {
- ext |= RVC;
- }
- if (riscv_has_ext(env, RVS)) {
- ext |= RVS;
- }
- if (riscv_has_ext(env, RVU)) {
- ext |= RVU;
- }
- if (riscv_has_ext(env, RVH)) {
- ext |= RVH;
- }
- if (riscv_has_ext(env, RVV)) {
- ext |= RVV;
- }
- if (riscv_has_ext(env, RVJ)) {
- ext |= RVJ;
- }
-
- env->misa_ext = env->misa_ext_mask = ext;
-}
-
static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
{
if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -1228,14 +1184,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_priv_version(env, priv_version);
}
- /*
- * We can't be sure of whether we set defaults during cpu_init()
- * or whether the user enabled/disabled some bits via cpu->cfg
- * flags. Sync env->misa_ext with cpu->cfg now to allow us to
- * use just env->misa_ext later.
- */
- riscv_cpu_sync_misa_cfg(env);
-
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (48 preceding siblings ...)
2023-05-05 1:02 ` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Alistair Francis
` (40 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1ecb82bb5d..b005bcb786 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -403,11 +403,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, MXL_RV64, RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
- cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (49 preceding siblings ...)
2023-05-05 1:02 ` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Alistair Francis
` (39 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
and use riscv_has_ext(env, RVG).
The caveat is that we don't have RVG, so add it. RVG will be used right
off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
enabling G via the now removed 'ext_g' flag.
After this patch, there are no more MISA extensions represented by flags
in RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 17 ++++++++---------
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e011cf6ca4..070547234b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVJ RV('J')
+#define RVG RV('G')
/* Privileged specification version */
@@ -422,7 +423,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
- bool ext_g;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b005bcb786..143079a8df 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -403,10 +403,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVC | RVS | RVU);
+ set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
- cpu->cfg.ext_g = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;
@@ -814,12 +813,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
- riscv_has_ext(env, RVM) &&
- riscv_has_ext(env, RVA) &&
- riscv_has_ext(env, RVF) &&
- riscv_has_ext(env, RVD) &&
- cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+ if (riscv_has_ext(env, RVG) &&
+ !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
+ riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
+ riscv_has_ext(env, RVD) &&
+ cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -1462,6 +1460,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVJ, .enabled = false},
{.name = "v", .description = "Vector operations",
.misa_bit = RVV, .enabled = false},
+ {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)",
+ .misa_bit = RVG, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1484,7 +1484,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
- DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props()
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (50 preceding siblings ...)
2023-05-05 1:02 ` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Alistair Francis
` (38 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The function is now a no-op for all cpu_init() callers that are setting
a non-zero misa value in set_misa(), since it's no longer used to sync
cpu->cfg props with env->misa_ext bits. Remove it in those cases.
While we're at it, rename the function to match what it's actually
doing: create user properties to set/remove CPU extensions. Make a note
that it will overwrite env->misa_ext with the defaults set by each user
property.
Update the MISA bits comment in cpu.h as well.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +----
target/riscv/cpu.c | 41 ++++++++++-------------------------------
2 files changed, 11 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 070547234b..f47c3fc139 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -65,10 +65,7 @@
#define RV(x) ((target_ulong)1 << (x - 'A'))
-/*
- * Consider updating register_cpu_props() when adding
- * new MISA bits here.
- */
+/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 143079a8df..d1769fd218 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void register_cpu_props(Object *obj);
+static void riscv_cpu_add_user_properties(Object *obj);
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
@@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj)
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
- register_cpu_props(obj);
}
#if defined(TARGET_RISCV64)
@@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
- register_cpu_props(obj);
+ riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
- register_cpu_props(obj);
+ riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
- register_cpu_props(obj);
+ riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
#ifndef CONFIG_USER_ONLY
@@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
- register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
@@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
- register_cpu_props(obj);
+ riscv_cpu_add_user_properties(obj);
}
#endif
@@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] = {
};
/*
- * Register CPU props based on env.misa_ext. If a non-zero
- * value was set, register only the required cpu->cfg.ext_*
- * properties and leave. env.misa_ext = 0 means that we want
- * all the default properties to be registered.
+ * Add CPU properties with user-facing flags.
+ *
+ * This will overwrite existing env->misa_ext values with the
+ * defaults set via riscv_cpu_add_misa_properties().
*/
-static void register_cpu_props(Object *obj)
+static void riscv_cpu_add_user_properties(Object *obj)
{
- RISCVCPU *cpu = RISCV_CPU(obj);
Property *prop;
DeviceState *dev = DEVICE(obj);
- /*
- * If misa_ext is not zero, set cfg properties now to
- * allow them to be read during riscv_cpu_realize()
- * later on.
- */
- if (cpu->env.misa_ext != 0) {
- /*
- * We don't want to set the default riscv_cpu_extensions
- * in this case.
- */
- return;
- }
-
riscv_cpu_add_misa_properties(obj);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (51 preceding siblings ...)
2023-05-05 1:02 ` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Alistair Francis
` (37 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230407014743.18779-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ec9a384772..b8a03afebb 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -338,7 +338,8 @@ target_ulong helper_mret(CPURISCVState *env)
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
- mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+ mstatus = set_field(mstatus, MSTATUS_MPP,
+ riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (52 preceding siblings ...)
2023-05-05 1:02 ` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Alistair Francis
` (36 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Richard Henderson
From: Weiwei Li <liweiwei@iscas.ac.cn>
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu_bits.h | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/gdbstub.c | 2 +-
target/riscv/op_helper.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f47c3fc139..86e08d10da 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -684,7 +684,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
case PRV_U:
xl = get_field(env->mstatus, MSTATUS64_UXL);
break;
- default: /* PRV_S | PRV_H */
+ default: /* PRV_S */
xl = get_field(env->mstatus, MSTATUS64_SXL);
break;
}
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 101702cb4a..a16bfaf43f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -608,7 +608,7 @@ typedef enum {
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
-#define PRV_H 2 /* Reserved */
+#define PRV_RESERVED 2
#define PRV_M 3
/* RV32 satp CSR field masks */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2310c7905f..29ac7956f7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -650,7 +650,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
if (newpriv > PRV_M) {
g_assert_not_reached();
}
- if (newpriv == PRV_H) {
+ if (newpriv == PRV_RESERVED) {
newpriv = PRV_U;
}
if (icount_enabled() && newpriv != env->priv) {
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index fa537aed74..524bede865 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
if (n == 0) {
#ifndef CONFIG_USER_ONLY
cs->priv = ldtul_p(mem_buf) & 0x3;
- if (cs->priv == PRV_H) {
+ if (cs->priv == PRV_RESERVED) {
cs->priv = PRV_S;
}
#endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b8a03afebb..bd21c6eeef 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -141,7 +141,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
}
if (env->virt_enabled &&
- (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
+ (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||
((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (53 preceding siblings ...)
2023-05-05 1:02 ` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Alistair Francis
` (35 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Richard Henderson
From: Weiwei Li <liweiwei@iscas.ac.cn>
mstatus.MPP field is a WARL field since priv version 1.11, so we
remain it unchanged if an invalid value is written into it. And
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 8 ++------
target/riscv/csr.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 29ac7956f7..433ea529b0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -647,12 +647,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
- if (newpriv > PRV_M) {
- g_assert_not_reached();
- }
- if (newpriv == PRV_RESERVED) {
- newpriv = PRV_U;
- }
+ g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
+
if (icount_enabled() && newpriv != env->priv) {
riscv_itrigger_update_priv(env);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0b871f6dc..f4d2dcfdc8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1230,6 +1230,32 @@ static bool validate_vm(CPURISCVState *env, target_ulong vm)
satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
}
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
+ target_ulong val)
+{
+ bool valid = false;
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+
+ switch (new_mpp) {
+ case PRV_M:
+ valid = true;
+ break;
+ case PRV_S:
+ valid = riscv_has_ext(env, RVS);
+ break;
+ case PRV_U:
+ valid = riscv_has_ext(env, RVU);
+ break;
+ }
+
+ /* Remain field unchanged if new_mpp value is invalid */
+ if (!valid) {
+ val = set_field(val, MSTATUS_MPP, old_mpp);
+ }
+
+ return val;
+}
+
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
@@ -1237,6 +1263,12 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
uint64_t mask = 0;
RISCVMXL xl = riscv_cpu_mxl(env);
+ /*
+ * MPP field have been made WARL since priv version 1.11. However,
+ * legalization for it will not break any software running on 1.10.
+ */
+ val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
+
/* flush tlb on mstatus fields that affect VM */
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (54 preceding siblings ...)
2023-05-05 1:02 ` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 57/89] target/riscv: fix H extension TVM trap Alistair Francis
` (34 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
by check currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d1769fd218..fab38859ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -916,8 +916,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zhinxmin = true;
}
- if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
- cpu->cfg.ext_zfinx = true;
+ if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+ error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
+ return;
}
if (cpu->cfg.ext_zfinx) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 57/89] target/riscv: fix H extension TVM trap
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (55 preceding siblings ...)
2023-05-05 1:02 ` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Alistair Francis
` (33 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Yi Chen, Weiwei Li, LIU Zhiwei, Alistair Francis
From: Yi Chen <chenyi2000@zju.edu.cn>
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with
HSTATUS.VTVM enabled.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA.
Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 56 +++++++++++++++++++++++++---------------
target/riscv/op_helper.c | 12 ++++-----
2 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f4d2dcfdc8..d2271da137 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -449,6 +449,30 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
return sstc(env, csrno);
}
+static RISCVException satp(CPURISCVState *env, int csrno)
+{
+ if (env->priv == PRV_S && !env->virt_enabled &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (env->priv == PRV_S && env->virt_enabled &&
+ get_field(env->hstatus, HSTATUS_VTVM)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+
+ return smode(env, csrno);
+}
+
+static RISCVException hgatp(CPURISCVState *env, int csrno)
+{
+ if (env->priv == PRV_S && !env->virt_enabled &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return hmode(env, csrno);
+}
+
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
@@ -2679,13 +2703,7 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
*val = 0;
return RISCV_EXCP_NONE;
}
-
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- } else {
- *val = env->satp;
- }
-
+ *val = env->satp;
return RISCV_EXCP_NONE;
}
@@ -2708,18 +2726,14 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
}
if (vm && mask) {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- } else {
- /*
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
- * pass these through QEMU's TLB emulation as it improves
- * performance. Flushing the TLB on SATP writes with paging
- * enabled avoids leaking those invalid cached mappings.
- */
- tlb_flush(env_cpu(env));
- env->satp = val;
- }
+ /*
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
+ * pass these through QEMU's TLB emulation as it improves
+ * performance. Flushing the TLB on SATP writes with paging
+ * enabled avoids leaking those invalid cached mappings.
+ */
+ tlb_flush(env_cpu(env));
+ env->satp = val;
}
return RISCV_EXCP_NONE;
}
@@ -4215,7 +4229,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Supervisor Protection and Translation */
- [CSR_SATP] = { "satp", smode, read_satp, write_satp },
+ [CSR_SATP] = { "satp", satp, read_satp, write_satp },
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
[CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
@@ -4252,7 +4266,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
.min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
+ [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta,
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index bd21c6eeef..0c10dd7a78 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -381,12 +381,12 @@ void helper_wfi(CPURISCVState *env)
void helper_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
- if (!(env->priv >= PRV_S) ||
- (env->priv == PRV_S &&
- get_field(env->mstatus, MSTATUS_TVM))) {
+ if (!env->virt_enabled &&
+ (env->priv == PRV_U ||
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
- } else if (riscv_has_ext(env, RVH) && env->virt_enabled &&
- get_field(env->hstatus, HSTATUS_VTVM)) {
+ } else if (env->virt_enabled &&
+ (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
tlb_flush(cs);
@@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
- if (env->priv == PRV_S && env->virt_enabled) {
+ if (env->virt_enabled) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 58/89] target/riscv: Extract virt enabled state from tb flags
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (56 preceding siblings ...)
2023-05-05 1:02 ` [PULL 57/89] target/riscv: fix H extension TVM trap Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 59/89] target/riscv: Add a general status enum for extensions Alistair Francis
` (32 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Richard Henderson, Weiwei Li,
Alistair Francis, Daniel Henrique Barboza
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 1 +
target/riscv/translate.c | 10 +---------
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86e08d10da..aa53d0e256 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -648,6 +648,8 @@ FIELD(TB_FLAGS, VTA, 24, 1)
FIELD(TB_FLAGS, VMA, 25, 1)
/* Native debug itrigger */
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
+/* Virtual mode enabled */
+FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 433ea529b0..1d90977d46 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -104,6 +104,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
get_field(env->mstatus_hs, MSTATUS_VS));
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled);
}
if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0094922b6..ebd00529ff 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1171,15 +1171,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->priv_ver = env->priv_ver;
-#if !defined(CONFIG_USER_ONLY)
- if (riscv_has_ext(env, RVH)) {
- ctx->virt_enabled = env->virt_enabled;
- } else {
- ctx->virt_enabled = false;
- }
-#else
- ctx->virt_enabled = false;
-#endif
+ ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 59/89] target/riscv: Add a general status enum for extensions
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (57 preceding siblings ...)
2023-05-05 1:02 ` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Alistair Francis
` (31 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Richard Henderson, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 8 ++++++++
target/riscv/cpu_bits.h | 12 ++++--------
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 14 +++++++-------
4 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index aa53d0e256..ba11279716 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,6 +97,14 @@ enum {
TRANSLATE_G_STAGE_FAIL
};
+/* Extension context status */
+typedef enum {
+ EXT_STATUS_DISABLED = 0,
+ EXT_STATUS_INITIAL,
+ EXT_STATUS_CLEAN,
+ EXT_STATUS_DIRTY,
+} RISCVExtStatus;
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a16bfaf43f..fb63b8e125 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -9,6 +9,9 @@
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
(uint64_t)(mask)))
+/* Extension context status mask */
+#define EXT_STATUS_MASK 0x3ULL
+
/* Floating point round mode */
#define FSR_RD_SHIFT 5
#define FSR_RD (0x7 << FSR_RD_SHIFT)
@@ -735,13 +738,6 @@ typedef enum RISCVException {
#define PM_ENABLE 0x00000001ULL
#define PM_CURRENT 0x00000002ULL
#define PM_INSN 0x00000004ULL
-#define PM_XS_MASK 0x00000003ULL
-
-/* PointerMasking XS bits values */
-#define PM_EXT_DISABLE 0x00000000ULL
-#define PM_EXT_INITIAL 0x00000001ULL
-#define PM_EXT_CLEAN 0x00000002ULL
-#define PM_EXT_DIRTY 0x00000003ULL
/* Execution enviornment configuration bits */
#define MENVCFG_FIOM BIT(0)
@@ -781,7 +777,7 @@ typedef enum RISCVException {
#define S_OFFSET 5ULL
#define M_OFFSET 8ULL
-#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
#define U_PM_INSN (PM_INSN << U_OFFSET)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fab38859ec..32c04214a1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -759,7 +759,7 @@ static void riscv_cpu_reset_hold(Object *obj)
i++;
}
/* mmte is supposed to have pm.current hardwired to 1 */
- env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
+ env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
#endif
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2271da137..92ad54411b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3548,7 +3548,7 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
- env->mmte = wpri_val | PM_EXT_DIRTY;
+ env->mmte = wpri_val | EXT_STATUS_DIRTY;
riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -3628,7 +3628,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3656,7 +3656,7 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3684,7 +3684,7 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3708,7 +3708,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3736,7 +3736,7 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3764,7 +3764,7 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (58 preceding siblings ...)
2023-05-05 1:02 ` [PULL 59/89] target/riscv: Add a general status enum for extensions Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Alistair Francis
` (30 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Richard Henderson, Weiwei Li,
Alistair Francis, Daniel Henrique Barboza
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.
It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 15 ++++++------
target/riscv/cpu_helper.c | 11 +++++----
target/riscv/translate.c | 32 +++++++++++--------------
target/riscv/insn_trans/trans_rvf.c.inc | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++----
5 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ba11279716..51d39687fe 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -631,18 +631,17 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
-#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
-#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
-FIELD(TB_FLAGS, LMUL, 3, 3)
-FIELD(TB_FLAGS, SEW, 6, 3)
-/* Skip MSTATUS_VS (0x600) bits */
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
-FIELD(TB_FLAGS, VILL, 12, 1)
-/* Skip MSTATUS_FS (0x6000) bits */
+FIELD(TB_FLAGS, FS, 3, 2)
+/* Vector flags */
+FIELD(TB_FLAGS, VS, 5, 2)
+FIELD(TB_FLAGS, LMUL, 7, 3)
+FIELD(TB_FLAGS, SEW, 10, 3)
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
+FIELD(TB_FLAGS, VILL, 14, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1d90977d46..8412ef26ee 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -79,16 +79,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#ifdef CONFIG_USER_ONLY
- flags |= TB_FLAGS_MSTATUS_FS;
- flags |= TB_FLAGS_MSTATUS_VS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
+ flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
- flags |= env->mstatus & MSTATUS_FS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS,
+ get_field(env->mstatus, MSTATUS_FS));
}
-
if (riscv_cpu_vector_enabled(env)) {
- flags |= env->mstatus & MSTATUS_VS;
+ flags = FIELD_DP32(flags, TB_FLAGS, VS,
+ get_field(env->mstatus, MSTATUS_VS));
}
if (riscv_has_ext(env, RVH)) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ebd00529ff..411e771e6f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -64,10 +64,10 @@ typedef struct DisasContext {
RISCVMXL xl;
uint32_t misa_ext;
uint32_t opcode;
- uint32_t mstatus_fs;
- uint32_t mstatus_vs;
- uint32_t mstatus_hs_fs;
- uint32_t mstatus_hs_vs;
+ RISCVExtStatus mstatus_fs;
+ RISCVExtStatus mstatus_vs;
+ RISCVExtStatus mstatus_hs_fs;
+ RISCVExtStatus mstatus_hs_vs;
uint32_t mem_idx;
/*
* Remember the rounding mode encoded in the previous fp instruction,
@@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
#ifndef CONFIG_USER_ONLY
/*
- * The states of mstatus_fs are:
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
@@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx)
return;
}
- if (ctx->mstatus_fs != MSTATUS_FS) {
+ if (ctx->mstatus_fs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
- ctx->mstatus_fs = MSTATUS_FS;
+ ctx->mstatus_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
@@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
}
- if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
+ if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {
/* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_fs = MSTATUS_FS;
+ ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
@@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
#ifndef CONFIG_USER_ONLY
/*
- * The states of mstatus_vs are:
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
@@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx)
{
TCGv tmp;
- if (ctx->mstatus_vs != MSTATUS_VS) {
+ if (ctx->mstatus_vs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
- ctx->mstatus_vs = MSTATUS_VS;
+ ctx->mstatus_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
@@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx)
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
}
- if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
+ if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {
/* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_vs = MSTATUS_VS;
+ ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
@@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
- ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
- ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
+ ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
+ ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
ctx->priv_ver = env->priv_ver;
ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
ctx->misa_ext = env->misa_ext;
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 9e9fa2087a..b2de4fcf3f 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -19,7 +19,7 @@
*/
#define REQUIRE_FPU do {\
- if (ctx->mstatus_fs == 0) \
+ if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \
if (!ctx->cfg_ptr->ext_zfinx) \
return false; \
} while (0)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ca3c4c1a3d..ecbdf1b3d7 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, int8_t asize,
static bool require_rvv(DisasContext *s)
{
- return s->mstatus_vs != 0;
+ return s->mstatus_vs != EXT_STATUS_DISABLED;
}
static bool require_rvf(DisasContext *s)
{
- if (s->mstatus_fs == 0) {
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
@@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s)
static bool require_scale_rvf(DisasContext *s)
{
- if (s->mstatus_fs == 0) {
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
@@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s)
static bool require_scale_rvfmin(DisasContext *s)
{
- if (s->mstatus_fs == 0) {
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (59 preceding siblings ...)
2023-05-05 1:02 ` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 62/89] target/riscv: Add a tb flags field for vstart Alistair Francis
` (29 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, LIU Zhiwei, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 16 +++++++---------
target/riscv/cpu_helper.c | 33 ++++++++++++++++-----------------
target/riscv/translate.c | 32 ++++++++++----------------------
3 files changed, 33 insertions(+), 48 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51d39687fe..ab64d5f92d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -644,19 +644,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
FIELD(TB_FLAGS, VILL, 14, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
-FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
-FIELD(TB_FLAGS, XL, 20, 2)
+FIELD(TB_FLAGS, XL, 16, 2)
/* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
-FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
-FIELD(TB_FLAGS, VTA, 24, 1)
-FIELD(TB_FLAGS, VMA, 25, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
+FIELD(TB_FLAGS, VTA, 20, 1)
+FIELD(TB_FLAGS, VMA, 21, 1)
/* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 26, 1)
+FIELD(TB_FLAGS, ITRIGGER, 22, 1)
/* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
+FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8412ef26ee..e3e620137b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
-
+ RISCVExtStatus fs, vs;
uint32_t flags = 0;
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
@@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#ifdef CONFIG_USER_ONLY
- flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
- flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
+ fs = EXT_STATUS_DIRTY;
+ vs = EXT_STATUS_DIRTY;
#else
flags |= cpu_mmu_index(env, 0);
- if (riscv_cpu_fp_enabled(env)) {
- flags = FIELD_DP32(flags, TB_FLAGS, FS,
- get_field(env->mstatus, MSTATUS_FS));
- }
- if (riscv_cpu_vector_enabled(env)) {
- flags = FIELD_DP32(flags, TB_FLAGS, VS,
- get_field(env->mstatus, MSTATUS_VS));
- }
+ fs = get_field(env->mstatus, MSTATUS_FS);
+ vs = get_field(env->mstatus, MSTATUS_VS);
if (riscv_has_ext(env, RVH)) {
if (env->priv == PRV_M ||
@@ -100,18 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
- get_field(env->mstatus_hs, MSTATUS_FS));
-
- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
- get_field(env->mstatus_hs, MSTATUS_VS));
- flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled);
+ if (env->virt_enabled) {
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
+ /*
+ * Merge DISABLED and !DIRTY states using MIN.
+ * We will set both fields when dirtying.
+ */
+ fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
+ vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
+ }
}
if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
}
#endif
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
+ flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 411e771e6f..3092c942ab 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -66,8 +66,6 @@ typedef struct DisasContext {
uint32_t opcode;
RISCVExtStatus mstatus_fs;
RISCVExtStatus mstatus_vs;
- RISCVExtStatus mstatus_hs_fs;
- RISCVExtStatus mstatus_hs_vs;
uint32_t mem_idx;
/*
* Remember the rounding mode encoded in the previous fp instruction,
@@ -620,16 +618,12 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- }
-
- if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {
- /* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
- tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
}
}
#else
@@ -653,16 +647,12 @@ static void mark_vs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- }
-
- if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {
- /* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
- tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
}
}
#else
@@ -1171,8 +1161,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
- ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
- ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 62/89] target/riscv: Add a tb flags field for vstart
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (60 preceding siblings ...)
2023-05-05 1:02 ` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 63/89] target/riscv: Separate priv from mmu_idx Alistair Francis
` (28 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, LIU Zhiwei, Richard Henderson, Weiwei Li,
Alistair Francis, Daniel Henrique Barboza
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 1 +
target/riscv/translate.c | 4 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 14 +++++++-------
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ab64d5f92d..786ad047ee 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -655,6 +655,7 @@ FIELD(TB_FLAGS, VMA, 21, 1)
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
/* Virtual mode enabled */
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
+FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e3e620137b..7579e83c3d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -74,6 +74,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
FIELD_EX64(env->vtype, VTYPE, VTA));
flags = FIELD_DP32(flags, TB_FLAGS, VMA,
FIELD_EX64(env->vtype, VTYPE, VMA));
+ flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3092c942ab..3ab8a9999e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -99,7 +99,7 @@ typedef struct DisasContext {
uint8_t vta;
uint8_t vma;
bool cfg_vta_all_1s;
- target_ulong vstart;
+ bool vstart_eq_zero;
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
@@ -1168,7 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
- ctx->vstart = env->vstart;
+ ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->misa_mxl_max = env->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ecbdf1b3d7..6c07eebc52 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -547,7 +547,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
*/
static bool vext_check_reduction(DisasContext *s, int vs2)
{
- return require_align(vs2, s->lmul) && (s->vstart == 0);
+ return require_align(vs2, s->lmul) && s->vstart_eq_zero;
}
/*
@@ -3083,7 +3083,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s) &&
- s->vstart == 0) {
+ s->vstart_eq_zero) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -3112,7 +3112,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s) &&
- s->vstart == 0) {
+ s->vstart_eq_zero) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -3148,7 +3148,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
vext_check_isa_ill(s) && \
require_vm(a->vm, a->rd) && \
(a->rd != a->rs2) && \
- (s->vstart == 0)) { \
+ s->vstart_eq_zero) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
@@ -3189,7 +3189,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
require_vm(a->vm, a->rd) &&
require_align(a->rd, s->lmul) &&
- (s->vstart == 0)) {
+ s->vstart_eq_zero) {
uint32_t data = 0;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -3638,7 +3638,7 @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a)
require_align(a->rs2, s->lmul) &&
(a->rd != a->rs2) &&
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) &&
- (s->vstart == 0);
+ s->vstart_eq_zero;
}
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
@@ -3677,7 +3677,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
QEMU_IS_ALIGNED(a->rd, LEN) && \
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
- if (s->vstart == 0) { \
+ if (s->vstart_eq_zero) { \
/* EEW = 8 */ \
tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 63/89] target/riscv: Separate priv from mmu_idx
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (61 preceding siblings ...)
2023-05-05 1:02 ` [PULL 62/89] target/riscv: Add a tb flags field for vstart Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Alistair Francis
` (27 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Fei Wu, Richard Henderson, LIU Zhiwei,
Alistair Francis, Weiwei Li, Daniel Henrique Barboza
From: Fei Wu <fei2.wu@intel.com>
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu_helper.c | 4 +++-
target/riscv/translate.c | 2 ++
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_xthead.c.inc | 14 +-------------
5 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 786ad047ee..9b971ee1b0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -629,7 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#include "exec/cpu-all.h"
@@ -656,6 +655,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1)
/* Virtual mode enabled */
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
+FIELD(TB_FLAGS, PRIV, 25, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7579e83c3d..36d6e422d7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -83,6 +83,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
fs = EXT_STATUS_DIRTY;
vs = EXT_STATUS_DIRTY;
#else
+ flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
+
flags |= cpu_mmu_index(env, 0);
fs = get_field(env->mstatus, MSTATUS_FS);
vs = get_field(env->mstatus, MSTATUS_VS);
@@ -751,7 +753,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*/
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
+ int mode = env->priv;
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3ab8a9999e..6d59348f0c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,6 +67,7 @@ typedef struct DisasContext {
RISCVExtStatus mstatus_fs;
RISCVExtStatus mstatus_vs;
uint32_t mem_idx;
+ uint32_t priv;
/*
* Remember the rounding mode encoded in the previous fp instruction,
* which we have already installed into env->fp_status. Or -1 for
@@ -1153,6 +1154,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_succ_insn = ctx->base.pc_first;
+ ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index e3bee971c6..7c2837194c 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -52,7 +52,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
* that no exception will be raised when fetching them.
*/
- if (semihosting_enabled(ctx->mem_idx < PRV_S) &&
+ if (semihosting_enabled(ctx->priv == PRV_U) &&
(pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
pre = opcode_at(&ctx->base, pre_addr);
ebreak = opcode_at(&ctx->base, ebreak_addr);
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index df504c3f2c..3e13b1d74d 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -263,25 +263,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
/* XTheadCmo */
-static inline int priv_level(DisasContext *ctx)
-{
-#ifdef CONFIG_USER_ONLY
- return PRV_U;
-#else
- /* Priv level is part of mem_idx. */
- return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
-#endif
-}
-
/* Test if priv level is M, S, or U (cannot fail). */
#define REQUIRE_PRIV_MSU(ctx)
/* Test if priv level is M or S. */
#define REQUIRE_PRIV_MS(ctx) \
do { \
- int priv = priv_level(ctx); \
- if (!(priv == PRV_M || \
- priv == PRV_S)) { \
+ if (ctx->priv == PRV_U) { \
return false; \
} \
} while (0)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (62 preceding siblings ...)
2023-05-05 1:02 ` [PULL 63/89] target/riscv: Separate priv from mmu_idx Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Alistair Francis
` (26 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Fei Wu, Richard Henderson, LIU Zhiwei,
Alistair Francis, Weiwei Li, Daniel Henrique Barboza
From: Fei Wu <fei2.wu@intel.com>
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a separate MMU index for S+SUM, so that it's not
necessary to flush tlb anymore when SUM changes. This is similar to how
ARM handles Privileged Access Never (PAN).
Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
other syscalls benefit a lot from this too.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 --
target/riscv/internals.h | 14 ++++++++++++++
target/riscv/cpu_helper.c | 17 +++++++++++++++--
target/riscv/csr.c | 3 +--
target/riscv/op_helper.c | 5 +++--
target/riscv/insn_trans/trans_rvh.c.inc | 4 ++--
6 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9b971ee1b0..6239c99f4c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -629,8 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
-
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 5620fbffb6..b55152a7dc 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -21,6 +21,20 @@
#include "hw/registerfields.h"
+/*
+ * The current MMU Modes are:
+ * - U 0b000
+ * - S 0b001
+ * - S+SUM 0b010
+ * - M 0b011
+ * - HLV/HLVX/HSV adds 0b100
+ */
+#define MMUIdx_U 0
+#define MMUIdx_S 1
+#define MMUIdx_S_SUM 2
+#define MMUIdx_M 3
+#define MMU_HYP_ACCESS_BIT (1 << 2)
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 36d6e422d7..174a77706b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "internals.h"
#include "pmu.h"
#include "exec/exec-all.h"
#include "instmap.h"
@@ -36,7 +37,19 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#ifdef CONFIG_USER_ONLY
return 0;
#else
- return env->priv;
+ if (ifetch) {
+ return env->priv;
+ }
+
+ /* All priv -> mmu_idx mapping are here */
+ int mode = env->priv;
+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
+ mode = get_field(env->mstatus, MSTATUS_MPP);
+ }
+ if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
+ return MMUIdx_S_SUM;
+ }
+ return mode;
#endif
}
@@ -588,7 +601,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
- return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ return mmu_idx & MMU_HYP_ACCESS_BIT;
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 92ad54411b..4a4d852bd1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1294,8 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
/* flush tlb on mstatus fields that affect VM */
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
- MSTATUS_MPRV | MSTATUS_SUM)) {
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 0c10dd7a78..0adfd1ca9a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "internals.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
@@ -428,14 +429,14 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
- int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
}
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
- int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
}
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 4b730cd492..ae98b45e5e 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -42,7 +42,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
if (check_access(ctx)) {
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);
}
@@ -89,7 +89,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
if (check_access(ctx)) {
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
}
return true;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (63 preceding siblings ...)
2023-05-05 1:02 ` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Alistair Francis
` (25 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Use the new functions to properly check execute permission
for the read rather than read permission.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 0adfd1ca9a..49179e7a5a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
+/*
+ * TODO: These implementations are not quite correct. They perform the
+ * access using execute permission just fine, but the final PMP check
+ * is supposed to have read permission as well. Without replicating
+ * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
+ * which would imply that exact check in tlb_fill.
+ */
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
- return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldw_code_mmu(env, address, oi, GETPC());
}
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
- return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldl_code_mmu(env, address, oi, GETPC());
}
#endif /* !CONFIG_USER_ONLY */
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 66/89] target/riscv: Handle HLV, HSV via helpers
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (64 preceding siblings ...)
2023-05-05 1:02 ` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Alistair Francis
` (24 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved out of line, which
allows HLSX to be removed from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 +-
target/riscv/helper.h | 12 ++-
target/riscv/cpu_helper.c | 26 ++---
target/riscv/op_helper.c | 99 ++++++++++++++++--
target/riscv/translate.c | 2 -
target/riscv/insn_trans/trans_rvh.c.inc | 129 ++++++++++--------------
6 files changed, 165 insertions(+), 109 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6239c99f4c..35cf2e2691 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -639,8 +639,7 @@ FIELD(TB_FLAGS, LMUL, 7, 3)
FIELD(TB_FLAGS, SEW, 10, 3)
FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
FIELD(TB_FLAGS, VILL, 14, 1)
-/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 15, 1)
+FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 16, 2)
/* If PointerMasking should be applied */
@@ -652,8 +651,7 @@ FIELD(TB_FLAGS, VMA, 21, 1)
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
/* Virtual mode enabled */
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
-FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1)
-FIELD(TB_FLAGS, PRIV, 25, 2)
+FIELD(TB_FLAGS, PRIV, 24, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1880e95c50..98e97810fd 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
-DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl)
-DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl)
+DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl)
#endif
/* Vector functions */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 174a77706b..abf275d2c6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -102,24 +102,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
fs = get_field(env->mstatus, MSTATUS_FS);
vs = get_field(env->mstatus, MSTATUS_VS);
- if (riscv_has_ext(env, RVH)) {
- if (env->priv == PRV_M ||
- (env->priv == PRV_S && !env->virt_enabled) ||
- (env->priv == PRV_U && !env->virt_enabled &&
- get_field(env->hstatus, HSTATUS_HU))) {
- flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
- }
-
- if (env->virt_enabled) {
- flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
- /*
- * Merge DISABLED and !DIRTY states using MIN.
- * We will set both fields when dirtying.
- */
- fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
- vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
- }
+ if (env->virt_enabled) {
+ flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
+ /*
+ * Merge DISABLED and !DIRTY states using MIN.
+ * We will set both fields when dirtying.
+ */
+ fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
+ vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
}
+
if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 49179e7a5a..7f83395370 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -427,6 +427,91 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
+static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
+{
+ if (env->priv == PRV_M) {
+ /* always allowed */
+ } else if (env->virt_enabled) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
+ } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
+ }
+
+ return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
+}
+
+target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+
+ return cpu_ldb_mmu(env, addr, oi, ra);
+}
+
+target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
+
+ return cpu_ldw_mmu(env, addr, oi, ra);
+}
+
+target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
+
+ return cpu_ldl_mmu(env, addr, oi, ra);
+}
+
+target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx);
+
+ return cpu_ldq_mmu(env, addr, oi, ra);
+}
+
+void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+
+ cpu_stb_mmu(env, addr, val, oi, ra);
+}
+
+void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
+
+ cpu_stw_mmu(env, addr, val, oi, ra);
+}
+
+void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
+
+ cpu_stl_mmu(env, addr, val, oi, ra);
+}
+
+void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val)
+{
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, false, ra);
+ MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx);
+
+ cpu_stq_mmu(env, addr, val, oi, ra);
+}
+
/*
* TODO: These implementations are not quite correct. They perform the
* access using execute permission just fine, but the final PMP check
@@ -434,20 +519,22 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
* a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
* which would imply that exact check in tlb_fill.
*/
-target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
+target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr)
{
- int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, true, ra);
MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
- return cpu_ldw_code_mmu(env, address, oi, GETPC());
+ return cpu_ldw_code_mmu(env, addr, oi, GETPC());
}
-target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
+target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr)
{
- int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ uintptr_t ra = GETPC();
+ int mmu_idx = check_access_hlsv(env, true, ra);
MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
- return cpu_ldl_code_mmu(env, address, oi, GETPC());
+ return cpu_ldl_code_mmu(env, addr, oi, ra);
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6d59348f0c..928da0d3f0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -80,7 +80,6 @@ typedef struct DisasContext {
bool virt_inst_excp;
bool virt_enabled;
const RISCVCPUConfig *cfg_ptr;
- bool hlsx;
/* vector extension */
bool vill;
/*
@@ -1163,7 +1162,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
- ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index ae98b45e5e..3e9322130f 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -16,158 +16,131 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef CONFIG_USER_ONLY
-static bool check_access(DisasContext *ctx)
-{
- if (!ctx->hlsx) {
- tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
- offsetof(CPURISCVState, bins));
- if (ctx->virt_enabled) {
- generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
- } else {
- generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
- }
- return false;
- }
+#ifdef CONFIG_USER_ONLY
+#define do_hlv(ctx, a, func) false
+#define do_hsv(ctx, a, func) false
+#else
+static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a)
+{
+ gen_helper_hyp_hlv_bu(r, e, a);
+ tcg_gen_ext8s_tl(r, r);
+}
+
+static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a)
+{
+ gen_helper_hyp_hlv_hu(r, e, a);
+ tcg_gen_ext16s_tl(r, r);
+}
+
+static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a)
+{
+ gen_helper_hyp_hlv_wu(r, e, a);
+ tcg_gen_ext32s_tl(r, r);
+}
+
+static bool do_hlv(DisasContext *ctx, arg_r2 *a,
+ void (*func)(TCGv, TCGv_env, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ decode_save_opc(ctx);
+ func(dest, cpu_env, addr);
+ gen_set_gpr(ctx, a->rd, dest);
return true;
}
-#endif
-static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
+static bool do_hsv(DisasContext *ctx, arg_r2_s *a,
+ void (*func)(TCGv_env, TCGv, TCGv))
{
-#ifdef CONFIG_USER_ONLY
- return false;
-#else
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
+
decode_save_opc(ctx);
- if (check_access(ctx)) {
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
- tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
- gen_set_gpr(ctx, a->rd, dest);
- }
+ func(cpu_env, addr, data);
return true;
-#endif
}
+#endif /* CONFIG_USER_ONLY */
static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_SB);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_b);
}
static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_TESW);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_h);
}
static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_TESL);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_w);
}
static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_UB);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_bu);
}
static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_TEUW);
-}
-
-static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
-{
-#ifdef CONFIG_USER_ONLY
- return false;
-#else
- decode_save_opc(ctx);
- if (check_access(ctx)) {
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT;
- tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
- }
- return true;
-#endif
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_hu);
}
static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hsv(ctx, a, MO_SB);
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_b);
}
static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hsv(ctx, a, MO_TESW);
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_h);
}
static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
{
REQUIRE_EXT(ctx, RVH);
- return do_hsv(ctx, a, MO_TESL);
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_w);
}
static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_TEUL);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_wu);
}
static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
- return do_hlv(ctx, a, MO_TEUQ);
+ return do_hlv(ctx, a, gen_helper_hyp_hlv_d);
}
static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVH);
- return do_hsv(ctx, a, MO_TEUQ);
-}
-
-#ifndef CONFIG_USER_ONLY
-static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
- void (*func)(TCGv, TCGv_env, TCGv))
-{
- decode_save_opc(ctx);
- if (check_access(ctx)) {
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- func(dest, cpu_env, addr);
- gen_set_gpr(ctx, a->rd, dest);
- }
- return true;
+ return do_hsv(ctx, a, gen_helper_hyp_hsv_d);
}
-#endif
static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
{
REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
- return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu);
-#else
- return false;
-#endif
+ return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu);
}
static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
{
REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
- return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu);
-#else
- return false;
-#endif
+ return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu);
}
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (65 preceding siblings ...)
2023-05-05 1:02 ` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 68/89] target/riscv: Introduce mmuidx_sum Alistair Francis
` (23 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 6 ++++--
target/riscv/cpu_helper.c | 2 +-
target/riscv/op_helper.c | 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b55152a7dc..7b63c0f1b6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,13 +27,15 @@
* - S 0b001
* - S+SUM 0b010
* - M 0b011
- * - HLV/HLVX/HSV adds 0b100
+ * - U+2STAGE 0b100
+ * - S+2STAGE 0b101
+ * - S+SUM+2STAGE 0b110
*/
#define MMUIdx_U 0
#define MMUIdx_S 1
#define MMUIdx_S_SUM 2
#define MMUIdx_M 3
-#define MMU_HYP_ACCESS_BIT (1 << 2)
+#define MMU_2STAGE_BIT (1 << 2)
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index abf275d2c6..291a1acbf7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
- return mmu_idx & MMU_HYP_ACCESS_BIT;
+ return mmu_idx & MMU_2STAGE_BIT;
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7f83395370..6122f5fbe5 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
- return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
+ return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 68/89] target/riscv: Introduce mmuidx_sum
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (66 preceding siblings ...)
2023-05-05 1:02 ` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 69/89] target/riscv: Introduce mmuidx_priv Alistair Francis
` (22 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 5 +++++
target/riscv/cpu_helper.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 7b63c0f1b6..0b61f337dd 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,11 @@
#define MMUIdx_M 3
#define MMU_2STAGE_BIT (1 << 2)
+static inline bool mmuidx_sum(int mmu_idx)
+{
+ return (mmu_idx & 3) == MMUIdx_S_SUM;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 291a1acbf7..29ee9b1b42 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -842,7 +842,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
widened = 2;
}
/* status.SUM will be ignored if execute on background */
- sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
+ sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 69/89] target/riscv: Introduce mmuidx_priv
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (67 preceding siblings ...)
2023-05-05 1:02 ` [PULL 68/89] target/riscv: Introduce mmuidx_sum Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 70/89] target/riscv: Introduce mmuidx_2stage Alistair Francis
` (21 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 9 +++++++++
target/riscv/cpu_helper.c | 6 +-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 0b61f337dd..4aa1cb409f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@
#define MMUIdx_M 3
#define MMU_2STAGE_BIT (1 << 2)
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
static inline bool mmuidx_sum(int mmu_idx)
{
return (mmu_idx & 3) == MMUIdx_S_SUM;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 29ee9b1b42..57bb19c76e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*/
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- int mode = env->priv;
+ int mode = mmuidx_priv(mmu_idx);
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
@@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*/
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
- } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
- }
}
if (first_stage == false) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 70/89] target/riscv: Introduce mmuidx_2stage
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (68 preceding siblings ...)
2023-05-05 1:02 ` [PULL 69/89] target/riscv: Introduce mmuidx_priv Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Alistair Francis
` (20 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/internals.h | 5 +++++
target/riscv/cpu_helper.c | 20 ++++++--------------
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 35cf2e2691..d1f888a790 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -581,7 +581,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 4aa1cb409f..b5f823c7ec 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx)
return (mmu_idx & 3) == MMUIdx_S_SUM;
}
+static inline bool mmuidx_2stage(int mmu_idx)
+{
+ return mmu_idx & MMU_2STAGE_BIT;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57bb19c76e..9dfd1d739b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
}
}
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
-{
- return mmu_idx & MMU_2STAGE_BIT;
-}
-
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env = &cpu->env;
@@ -779,7 +774,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
}
@@ -1175,8 +1170,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1201,8 +1195,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1256,7 +1249,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
@@ -1268,7 +1261,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
pmu_tlb_fill_incr_ctr(cpu, access_type);
if (env->virt_enabled ||
- ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+ ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
@@ -1366,8 +1359,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else {
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
- env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx),
+ env->virt_enabled || mmuidx_2stage(mmu_idx),
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (69 preceding siblings ...)
2023-05-05 1:02 ` [PULL 70/89] target/riscv: Introduce mmuidx_2stage Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Alistair Francis
` (19 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup. Provide the correct priv level directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 10 +---------
target/riscv/op_helper.c | 2 +-
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9dfd1d739b..ccba3c45e7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true;
}
- /*
- * MPRV does not affect the virtual-machine load/store
- * instructions, HLV, HLVX, and HSV.
- */
- if (mmuidx_2stage(mmu_idx)) {
- mode = get_field(env->hstatus, HSTATUS_SPVP);
- }
-
if (first_stage == false) {
/*
* We are in stage 2 translation, this is similar to stage 1.
@@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* instructions, HLV, HLVX, and HSV.
*/
if (mmuidx_2stage(mmu_idx)) {
- mode = get_field(env->hstatus, HSTATUS_SPVP);
+ ;
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6122f5fbe5..f83f7b5347 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
- return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
+ return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (70 preceding siblings ...)
2023-05-05 1:02 ` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 73/89] target/riscv: Check SUM in the correct register Alistair Francis
` (18 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
function, so we don't have to keep doing it within tlb_fill and
subroutines. This also elides a flush on changes to MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 49 ++++++++++++++-------------------------
target/riscv/csr.c | 6 +----
2 files changed, 18 insertions(+), 37 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ccba3c45e7..baa4b3a1d2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -37,19 +37,21 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#ifdef CONFIG_USER_ONLY
return 0;
#else
- if (ifetch) {
- return env->priv;
- }
+ bool virt = env->virt_enabled;
+ int mode = env->priv;
/* All priv -> mmu_idx mapping are here */
- int mode = env->priv;
- if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
- }
- if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
- return MMUIdx_S_SUM;
+ if (!ifetch) {
+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
+ mode = get_field(env->mstatus, MSTATUS_MPP);
+ virt = get_field(env->mstatus, MSTATUS_MPV);
+ }
+ if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
+ mode = MMUIdx_S_SUM;
+ }
}
- return mode;
+
+ return mode | (virt ? MMU_2STAGE_BIT : 0);
#endif
}
@@ -1162,7 +1164,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
+ env->two_stage_lookup = mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1187,7 +1189,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
+ env->two_stage_lookup = mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -1225,7 +1227,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
int prot, prot2, prot_pmp;
bool pmp_violation = false;
bool first_stage_error = true;
- bool two_stage_lookup = false;
+ bool two_stage_lookup = mmuidx_2stage(mmu_idx);
bool two_stage_indirect_error = false;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
@@ -1237,24 +1239,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /*
- * MPRV does not affect the virtual-machine load/store
- * instructions, HLV, HLVX, and HSV.
- */
- if (mmuidx_2stage(mmu_idx)) {
- ;
- } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
- if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
- two_stage_lookup = true;
- }
- }
-
pmu_tlb_fill_incr_ctr(cpu, access_type);
- if (env->virt_enabled ||
- ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
- access_type != MMU_INST_FETCH)) {
+ if (two_stage_lookup) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
&env->guest_phys_fault_addr, access_type,
@@ -1350,8 +1336,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
} else {
raise_mmu_exception(env, address, access_type, pmp_violation,
- first_stage_error,
- env->virt_enabled || mmuidx_2stage(mmu_idx),
+ first_stage_error, two_stage_lookup,
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4a4d852bd1..865ee9efda 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1294,7 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
/* flush tlb on mstatus fields that affect VM */
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
+ if ((val ^ mstatus) & MSTATUS_MXR) {
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
@@ -1342,10 +1342,6 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
uint64_t valh = (uint64_t)val << 32;
uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
- if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
- tlb_flush(env_cpu(env));
- }
-
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
return RISCV_EXCP_NONE;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 73/89] target/riscv: Check SUM in the correct register
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (71 preceding siblings ...)
2023-05-05 1:02 ` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 74/89] target/riscv: Hoist second stage mode change to callers Alistair Francis
` (17 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
vsstatus.SUM instead of HS-level sstatus.SUM.
For HLV/HSV instructions, the HS-level register does not apply, but
the VS-level register presumably does, though this is not mentioned
explicitly in the manual. However, it matches the behavior for MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 ++++++++----
target/riscv/op_helper.c | 6 +++++-
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index baa4b3a1d2..38bd83f66d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -42,11 +42,16 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
/* All priv -> mmu_idx mapping are here */
if (!ifetch) {
- if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
+ uint64_t status = env->mstatus;
+
+ if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
virt = get_field(env->mstatus, MSTATUS_MPV);
+ if (virt) {
+ status = env->vsstatus;
+ }
}
- if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
+ if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {
mode = MMUIdx_S_SUM;
}
}
@@ -826,8 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 2;
}
- /* status.SUM will be ignored if execute on background */
- sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
+ sum = mmuidx_sum(mmu_idx) || is_debug;
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f83f7b5347..f563dc3981 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -437,7 +437,11 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
- return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT;
+ int mode = get_field(env->hstatus, HSTATUS_SPVP);
+ if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) {
+ mode = MMUIdx_S_SUM;
+ }
+ return mode | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 74/89] target/riscv: Hoist second stage mode change to callers
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (72 preceding siblings ...)
2023-05-05 1:02 ` [PULL 73/89] target/riscv: Check SUM in the correct register Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Alistair Francis
` (16 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 38bd83f66d..5753e4e612 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true;
}
- if (first_stage == false) {
- /*
- * We are in stage 2 translation, this is similar to stage 1.
- * Stage 2 is always taken as U-mode
- */
- mode = PRV_U;
- }
-
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -890,7 +882,7 @@ restart:
/* Do the second stage translation on the base PTE address. */
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
base, NULL, MMU_DATA_LOAD,
- mmu_idx, false, true,
+ MMUIdx_U, false, true,
is_debug);
if (vbase_ret != TRANSLATE_SUCCESS) {
@@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
im_address = pa;
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
- access_type, mmu_idx, false, true,
+ access_type, MMUIdx_U, false, true,
false);
qemu_log_mask(CPU_LOG_MMU,
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (73 preceding siblings ...)
2023-05-05 1:02 ` [PULL 74/89] target/riscv: Hoist second stage mode change to callers Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 76/89] target/riscv: Move leaf pte processing out of " Alistair Francis
` (15 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5753e4e612..7c9f89d4d3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -856,6 +856,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
return TRANSLATE_FAIL;
}
+ bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+ bool hade = env->menvcfg & MENVCFG_HADE;
+
+ if (first_stage && two_stage && env->virt_enabled) {
+ pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+ hade = hade && (env->henvcfg & HENVCFG_HADE);
+ }
+
int ptshift = (levels - 1) * ptidxbits;
int i;
@@ -916,14 +924,6 @@ restart:
return TRANSLATE_FAIL;
}
- bool pbmte = env->menvcfg & MENVCFG_PBMTE;
- bool hade = env->menvcfg & MENVCFG_HADE;
-
- if (first_stage && two_stage && env->virt_enabled) {
- pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
- hade = hade && (env->henvcfg & HENVCFG_HADE);
- }
-
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 76/89] target/riscv: Move leaf pte processing out of level loop
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (74 preceding siblings ...)
2023-05-05 1:02 ` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 77/89] target/riscv: Suppress pte update with is_debug Alistair Francis
` (14 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Move the code that never loops outside of the loop.
Unchain the if-return-else statements.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 234 ++++++++++++++++++++------------------
1 file changed, 123 insertions(+), 111 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7c9f89d4d3..c2d083f029 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -865,6 +865,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
int ptshift = (levels - 1) * ptidxbits;
+ target_ulong pte;
+ hwaddr pte_addr;
int i;
#if !TCG_OVERSIZED_GUEST
@@ -881,7 +883,6 @@ restart:
}
/* check that physical address of PTE is legal */
- hwaddr pte_addr;
if (two_stage && first_stage) {
int vbase_prot;
@@ -913,7 +914,6 @@ restart:
return TRANSLATE_PMP_FAIL;
}
- target_ulong pte;
if (riscv_cpu_mxl(env) == MXL_RV32) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
@@ -938,128 +938,140 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
- } else if (!pbmte && (pte & PTE_PBMT)) {
- return TRANSLATE_FAIL;
- } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
- /* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
- return TRANSLATE_FAIL;
- }
- base = ppn << PGSHIFT;
- } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
- /* Reserved leaf PTE flags: PTE_W */
- return TRANSLATE_FAIL;
- } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
- /* Reserved leaf PTE flags: PTE_W + PTE_X */
- return TRANSLATE_FAIL;
- } else if ((pte & PTE_U) && ((mode != PRV_U) &&
- (!sum || access_type == MMU_INST_FETCH))) {
- /* User PTE flags when not U mode and mstatus.SUM is not set,
- or the access type is an instruction fetch */
- return TRANSLATE_FAIL;
- } else if (!(pte & PTE_U) && (mode != PRV_S)) {
- /* Supervisor PTE flags when not S mode */
- return TRANSLATE_FAIL;
- } else if (ppn & ((1ULL << ptshift) - 1)) {
- /* Misaligned PPN */
- return TRANSLATE_FAIL;
- } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
- ((pte & PTE_X) && mxr))) {
- /* Read access check failed */
- return TRANSLATE_FAIL;
- } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
- /* Write access check failed */
- return TRANSLATE_FAIL;
- } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
- /* Fetch access check failed */
+ }
+ if (pte & (PTE_R | PTE_W | PTE_X)) {
+ goto leaf;
+ }
+
+ /* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
return TRANSLATE_FAIL;
- } else {
- /* if necessary, set accessed and dirty bits. */
- target_ulong updated_pte = pte | PTE_A |
+ }
+ base = ppn << PGSHIFT;
+ }
+
+ /* No leaf pte at any translation level. */
+ return TRANSLATE_FAIL;
+
+ leaf:
+ if (ppn & ((1ULL << ptshift) - 1)) {
+ /* Misaligned PPN */
+ return TRANSLATE_FAIL;
+ }
+ if (!pbmte && (pte & PTE_PBMT)) {
+ /* Reserved without Svpbmt. */
+ return TRANSLATE_FAIL;
+ }
+ if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
+ /* Reserved leaf PTE flags: PTE_W */
+ return TRANSLATE_FAIL;
+ }
+ if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
+ /* Reserved leaf PTE flags: PTE_W + PTE_X */
+ return TRANSLATE_FAIL;
+ }
+ if ((pte & PTE_U) &&
+ ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
+ /*
+ * User PTE flags when not U mode and mstatus.SUM is not set,
+ * or the access type is an instruction fetch.
+ */
+ return TRANSLATE_FAIL;
+ }
+ if (!(pte & PTE_U) && (mode != PRV_S)) {
+ /* Supervisor PTE flags when not S mode */
+ return TRANSLATE_FAIL;
+ }
+ if (access_type == MMU_DATA_LOAD &&
+ !((pte & PTE_R) || ((pte & PTE_X) && mxr))) {
+ /* Read access check failed */
+ return TRANSLATE_FAIL;
+ }
+ if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
+ /* Write access check failed */
+ return TRANSLATE_FAIL;
+ }
+ if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
+ /* Fetch access check failed */
+ return TRANSLATE_FAIL;
+ }
+
+ /* If necessary, set accessed and dirty bits. */
+ target_ulong updated_pte = pte | PTE_A |
(access_type == MMU_DATA_STORE ? PTE_D : 0);
- /* Page table updates need to be atomic with MTTCG enabled */
- if (updated_pte != pte) {
- if (!hade) {
- return TRANSLATE_FAIL;
- }
+ /* Page table updates need to be atomic with MTTCG enabled */
+ if (updated_pte != pte) {
+ if (!hade) {
+ return TRANSLATE_FAIL;
+ }
- /*
- * - if accessed or dirty bits need updating, and the PTE is
- * in RAM, then we do so atomically with a compare and swap.
- * - if the PTE is in IO space or ROM, then it can't be updated
- * and we return TRANSLATE_FAIL.
- * - if the PTE changed by the time we went to update it, then
- * it is no longer valid and we must re-walk the page table.
- */
- MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
- mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
- false, MEMTXATTRS_UNSPECIFIED);
- if (memory_region_is_ram(mr)) {
- target_ulong *pte_pa =
- qemu_map_ram_ptr(mr->ram_block, addr1);
+ /*
+ * - if accessed or dirty bits need updating, and the PTE is
+ * in RAM, then we do so atomically with a compare and swap.
+ * - if the PTE is in IO space or ROM, then it can't be updated
+ * and we return TRANSLATE_FAIL.
+ * - if the PTE changed by the time we went to update it, then
+ * it is no longer valid and we must re-walk the page table.
+ */
+ MemoryRegion *mr;
+ hwaddr l = sizeof(target_ulong), addr1;
+ mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
+ false, MEMTXATTRS_UNSPECIFIED);
+ if (memory_region_is_ram(mr)) {
+ target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
- /*
- * MTTCG is not enabled on oversized TCG guests so
- * page table updates do not need to be atomic
- */
- *pte_pa = pte = updated_pte;
+ /*
+ * MTTCG is not enabled on oversized TCG guests so
+ * page table updates do not need to be atomic
+ */
+ *pte_pa = pte = updated_pte;
#else
- target_ulong old_pte =
- qatomic_cmpxchg(pte_pa, pte, updated_pte);
- if (old_pte != pte) {
- goto restart;
- } else {
- pte = updated_pte;
- }
-#endif
- } else {
- /*
- * misconfigured PTE in ROM (AD bits are not preset) or
- * PTE is in IO space and can't be updated atomically
- */
- return TRANSLATE_FAIL;
- }
+ target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ if (old_pte != pte) {
+ goto restart;
}
-
+ pte = updated_pte;
+#endif
+ } else {
/*
- * for superpage mappings, make a fake leaf PTE for the TLB's
- * benefit.
+ * Misconfigured PTE in ROM (AD bits are not preset) or
+ * PTE is in IO space and can't be updated atomically.
*/
- target_ulong vpn = addr >> PGSHIFT;
-
- if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
- napot_bits = ctzl(ppn) + 1;
- if ((i != (levels - 1)) || (napot_bits != 4)) {
- return TRANSLATE_FAIL;
- }
- }
+ return TRANSLATE_FAIL;
+ }
+ }
- napot_mask = (1 << napot_bits) - 1;
- *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
- (vpn & (((target_ulong)1 << ptshift) - 1))
- ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
+ /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
+ target_ulong vpn = addr >> PGSHIFT;
- /* set permissions on the TLB entry */
- if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
- *prot |= PAGE_READ;
- }
- if (pte & PTE_X) {
- *prot |= PAGE_EXEC;
- }
- /*
- * add write permission on stores or if the page is already dirty,
- * so that we TLB miss on later writes to update the dirty bit
- */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
- *prot |= PAGE_WRITE;
- }
- return TRANSLATE_SUCCESS;
+ if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
+ napot_bits = ctzl(ppn) + 1;
+ if ((i != (levels - 1)) || (napot_bits != 4)) {
+ return TRANSLATE_FAIL;
}
}
- return TRANSLATE_FAIL;
+
+ napot_mask = (1 << napot_bits) - 1;
+ *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
+
+ /* set permissions on the TLB entry */
+ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
+ *prot |= PAGE_READ;
+ }
+ if (pte & PTE_X) {
+ *prot |= PAGE_EXEC;
+ }
+ /*
+ * Add write permission on stores or if the page is already dirty,
+ * so that we TLB miss on later writes to update the dirty bit.
+ */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ *prot |= PAGE_WRITE;
+ }
+ return TRANSLATE_SUCCESS;
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 77/89] target/riscv: Suppress pte update with is_debug
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (75 preceding siblings ...)
2023-05-05 1:02 ` [PULL 76/89] target/riscv: Move leaf pte processing out of " Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 78/89] target/riscv: Don't modify SUM " Alistair Francis
` (13 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
The debugger should not modify PTE_A or PTE_D.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c2d083f029..6dc3fdf594 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1001,7 +1001,7 @@ restart:
(access_type == MMU_DATA_STORE ? PTE_D : 0);
/* Page table updates need to be atomic with MTTCG enabled */
- if (updated_pte != pte) {
+ if (updated_pte != pte && !is_debug) {
if (!hade) {
return TRANSLATE_FAIL;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 78/89] target/riscv: Don't modify SUM with is_debug
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (76 preceding siblings ...)
2023-05-05 1:02 ` [PULL 77/89] target/riscv: Suppress pte update with is_debug Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 79/89] target/riscv: Merge checks for reserved pte flags Alistair Francis
` (12 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
If we want to give the debugger a greater view of memory than
the cpu, we should simply disable the access check entirely,
not simply for this one corner case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6dc3fdf594..9a2b944990 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -823,7 +823,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 2;
}
- sum = mmuidx_sum(mmu_idx) || is_debug;
+ sum = mmuidx_sum(mmu_idx);
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 79/89] target/riscv: Merge checks for reserved pte flags
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (77 preceding siblings ...)
2023-05-05 1:02 ` [PULL 78/89] target/riscv: Don't modify SUM " Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 80/89] target/riscv: Reorg access check in get_physical_address Alistair Francis
` (11 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9a2b944990..c7c384bae3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -962,14 +962,14 @@ restart:
/* Reserved without Svpbmt. */
return TRANSLATE_FAIL;
}
- if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
- /* Reserved leaf PTE flags: PTE_W */
- return TRANSLATE_FAIL;
- }
- if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
- /* Reserved leaf PTE flags: PTE_W + PTE_X */
+
+ /* Check for reserved combinations of RWX flags. */
+ switch (pte & (PTE_R | PTE_W | PTE_X)) {
+ case PTE_W:
+ case PTE_W | PTE_X:
return TRANSLATE_FAIL;
}
+
if ((pte & PTE_U) &&
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
/*
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 80/89] target/riscv: Reorg access check in get_physical_address
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (78 preceding siblings ...)
2023-05-05 1:02 ` [PULL 79/89] target/riscv: Merge checks for reserved pte flags Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 81/89] target/riscv: Reorg sum " Alistair Francis
` (10 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
We were effectively computing the protection bits twice,
once while performing access checks and once while returning
the valid bits to the caller. Reorg so we do this once.
Move the computation of mxr close to its single use.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 69 ++++++++++++++++++++-------------------
1 file changed, 36 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c7c384bae3..7849e18554 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -747,7 +747,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
* @is_debug: Is this access from a debugger or the monitor?
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
- int *prot, vaddr addr,
+ int *ret_prot, vaddr addr,
target_ulong *fault_pte_addr,
int access_type, int mmu_idx,
bool first_stage, bool two_stage,
@@ -779,20 +779,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
- *prot = 0;
+ *ret_prot = 0;
hwaddr base;
- int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
-
- if (first_stage == true) {
- mxr = get_field(env->mstatus, MSTATUS_MXR);
- } else {
- mxr = get_field(env->vsstatus, MSTATUS_MXR);
- }
+ int levels, ptidxbits, ptesize, vm, sum, widened;
if (first_stage == true) {
if (use_background) {
@@ -835,7 +829,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
levels = 5; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_MBARE:
*physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
default:
g_assert_not_reached();
@@ -970,6 +964,27 @@ restart:
return TRANSLATE_FAIL;
}
+ int prot = 0;
+ if (pte & PTE_R) {
+ prot |= PAGE_READ;
+ }
+ if (pte & PTE_W) {
+ prot |= PAGE_WRITE;
+ }
+ if (pte & PTE_X) {
+ bool mxr;
+
+ if (first_stage == true) {
+ mxr = get_field(env->mstatus, MSTATUS_MXR);
+ } else {
+ mxr = get_field(env->vsstatus, MSTATUS_MXR);
+ }
+ if (mxr) {
+ prot |= PAGE_READ;
+ }
+ prot |= PAGE_EXEC;
+ }
+
if ((pte & PTE_U) &&
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
/*
@@ -982,17 +997,9 @@ restart:
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
}
- if (access_type == MMU_DATA_LOAD &&
- !((pte & PTE_R) || ((pte & PTE_X) && mxr))) {
- /* Read access check failed */
- return TRANSLATE_FAIL;
- }
- if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
- /* Write access check failed */
- return TRANSLATE_FAIL;
- }
- if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
- /* Fetch access check failed */
+
+ if (!((prot >> access_type) & 1)) {
+ /* Access check failed */
return TRANSLATE_FAIL;
}
@@ -1057,20 +1064,16 @@ restart:
(vpn & (((target_ulong)1 << ptshift) - 1))
) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
- /* set permissions on the TLB entry */
- if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
- *prot |= PAGE_READ;
- }
- if (pte & PTE_X) {
- *prot |= PAGE_EXEC;
- }
/*
- * Add write permission on stores or if the page is already dirty,
- * so that we TLB miss on later writes to update the dirty bit.
+ * Remove write permission unless this is a store, or the page is
+ * already dirty, so that we TLB miss on later writes to update
+ * the dirty bit.
*/
- if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
- *prot |= PAGE_WRITE;
+ if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) {
+ prot &= ~PAGE_WRITE;
}
+ *ret_prot = prot;
+
return TRANSLATE_SUCCESS;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 81/89] target/riscv: Reorg sum check in get_physical_address
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (79 preceding siblings ...)
2023-05-05 1:02 ` [PULL 80/89] target/riscv: Reorg access check in get_physical_address Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Alistair Francis
` (9 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Richard Henderson, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza
From: Richard Henderson <richard.henderson@linaro.org>
Implement this by adjusting prot, which reduces the set of
checks required. This prevents exec to be set for U pages
in MMUIdx_S_SUM. While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7849e18554..32a65f8007 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -786,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*ret_prot = 0;
hwaddr base;
- int levels, ptidxbits, ptesize, vm, sum, widened;
+ int levels, ptidxbits, ptesize, vm, widened;
if (first_stage == true) {
if (use_background) {
@@ -817,7 +817,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 2;
}
- sum = mmuidx_sum(mmu_idx);
+
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -985,15 +985,15 @@ restart:
prot |= PAGE_EXEC;
}
- if ((pte & PTE_U) &&
- ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
- /*
- * User PTE flags when not U mode and mstatus.SUM is not set,
- * or the access type is an instruction fetch.
- */
- return TRANSLATE_FAIL;
- }
- if (!(pte & PTE_U) && (mode != PRV_S)) {
+ if (pte & PTE_U) {
+ if (mode != PRV_U) {
+ if (!mmuidx_sum(mmu_idx)) {
+ return TRANSLATE_FAIL;
+ }
+ /* SUM allows only read+write, not execute. */
+ prot &= PAGE_READ | PAGE_WRITE;
+ }
+ } else if (mode != PRV_S) {
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (80 preceding siblings ...)
2023-05-05 1:02 ` [PULL 81/89] target/riscv: Reorg sum " Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 83/89] target/riscv: add CPU QOM header Alistair Francis
` (8 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Ivan Klokov, Alistair Francis, Anup Patel
From: Ivan Klokov <ivan.klokov@syntacore.com>
Since g_new is used to initialize the RISCVAPLICState->state structure,
in some case we get behavior that is not as expected. This patch
changes this to g_new0, which allows to initialize the APLIC in the correct state.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230413133432.53771-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index cd7efc4ad4..afc5b54dbb 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -803,7 +803,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
- aplic->state = g_new(uint32_t, aplic->num_irqs);
+ aplic->state = g_new0(uint32_t, aplic->num_irqs);
aplic->target = g_new0(uint32_t, aplic->num_irqs);
if (!aplic->msimode) {
for (i = 0; i < aplic->num_irqs; i++) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 83/89] target/riscv: add CPU QOM header
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (81 preceding siblings ...)
2023-05-05 1:02 ` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 84/89] target/riscv: add query-cpy-definitions support Alistair Francis
` (7 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Richard Henderson, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
QMP CPU commands are usually implemented by a separated file,
<arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
This file uses a CPU QOM header with basic QOM declarations for the
arch.
We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
but first we need a cpu-qom.h header with the definitions of
TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 46 +--------------------------
2 files changed, 71 insertions(+), 45 deletions(-)
create mode 100644 target/riscv/cpu-qom.h
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
new file mode 100644
index 0000000000..b9318e0783
--- /dev/null
+++ b/target/riscv/cpu-qom.h
@@ -0,0 +1,70 @@
+/*
+ * QEMU RISC-V CPU QOM header
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_CPU_QOM_H
+#define RISCV_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_CPU "riscv-cpu"
+
+#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
+#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
+
+#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
+#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
+#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
+#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
+#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
+#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
+#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
+
+#if defined(TARGET_RISCV32)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
+#elif defined(TARGET_RISCV64)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#endif
+
+typedef struct CPUArchState CPURISCVState;
+
+OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
+
+/**
+ * RISCVCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RISCV CPU model.
+ */
+struct RISCVCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d1f888a790..de7e43126a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -28,6 +28,7 @@
#include "qemu/int128.h"
#include "cpu_bits.h"
#include "qapi/qapi-types-common.h"
+#include "cpu-qom.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -37,32 +38,6 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 1
-#define TYPE_RISCV_CPU "riscv-cpu"
-
-#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
-#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
-#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
-
-#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
-#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
-#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
-#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
-#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
-#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
-#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
-#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
-#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
-#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
-#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
-#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
-#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
-
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
-#endif
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
@@ -109,8 +84,6 @@ typedef enum {
#define MAX_RISCV_PMPS (16)
-typedef struct CPUArchState CPURISCVState;
-
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
#include "debug.h"
@@ -395,23 +368,6 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
-
-/*
- * RISCVCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RISCV CPU model.
- */
-struct RISCVCPUClass {
- /* < private > */
- CPUClass parent_class;
- /* < public > */
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
-
/*
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
* satp mode that is supported. It may be chosen by the user and must respect
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 84/89] target/riscv: add query-cpy-definitions support
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (82 preceding siblings ...)
2023-05-05 1:02 ` [PULL 83/89] target/riscv: add CPU QOM header Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Alistair Francis
` (6 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Richard Henderson, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This command is used by tooling like libvirt to retrieve a list of
supported CPUs. Each entry returns a CpuDefinitionInfo object that
contains more information about each CPU.
This initial support includes only the name of the CPU and its typename.
Here's what the command produces for the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}]
}
Next patch will introduce a way to tell whether a given CPU is static or
not.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
qapi/machine-target.json | 6 ++--
target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
3 files changed, 59 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/riscv-qmp-cmds.c
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index b94fbdb65e..afc8c40894 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -324,7 +324,8 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
- 'TARGET_LOONGARCH64' ] } }
+ 'TARGET_LOONGARCH64',
+ 'TARGET_RISCV' ] } }
##
# @query-cpu-definitions:
@@ -341,4 +342,5 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
- 'TARGET_LOONGARCH64' ] } }
+ 'TARGET_LOONGARCH64',
+ 'TARGET_RISCV' ] } }
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
new file mode 100644
index 0000000000..128677add9
--- /dev/null
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -0,0 +1,53 @@
+/*
+ * QEMU CPU QMP commands for RISC-V
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qapi/qapi-commands-machine-target.h"
+#include "cpu-qom.h"
+
+static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
+ const char *typename = object_class_get_name(oc);
+
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_RISCV_CPU));
+ info->q_typename = g_strdup(typename);
+
+ QAPI_LIST_PREPEND(*cpu_list, info);
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list = object_class_get_list(TYPE_RISCV_CPU, false);
+
+ g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 5b7f813a3e..e1ff6d9b95 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files(
'monitor.c',
'machine.c',
'pmu.c',
- 'time_helper.c'
+ 'time_helper.c',
+ 'riscv-qmp-cmds.c',
))
target_arch += {'riscv': riscv_ss}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (83 preceding siblings ...)
2023-05-05 1:02 ` [PULL 84/89] target/riscv: add query-cpy-definitions support Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
` (5 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Richard Henderson, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This new abstract type will be used to differentiate between static and
non-static CPUs in query-cpu-definitions.
All generic CPUs were changed to be of this type. Named CPUs are kept as
TYPE_RISCV_CPU and will still be considered static.
This is the output of query-cpu-definitions after this change for the
riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false}
]}
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 2 +-
target/riscv/cpu.c | 20 ++++++++++++++++----
target/riscv/riscv-qmp-cmds.c | 4 ++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b9318e0783..b29090ad86 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -23,6 +23,7 @@
#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
+#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
@@ -66,5 +67,4 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
-
#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32c04214a1..befa64528f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1788,6 +1788,13 @@ void riscv_cpu_list(void)
.instance_init = initfn \
}
+#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_DYNAMIC_CPU, \
+ .instance_init = initfn \
+ }
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
},
- DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+ {
+ .name = TYPE_RISCV_DYNAMIC_CPU,
+ .parent = TYPE_RISCV_CPU,
+ .abstract = true,
+ },
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(CONFIG_KVM)
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
#endif
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 128677add9..5ecff1afb3 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
const char *typename = object_class_get_name(oc);
+ ObjectClass *dyn_class;
info->name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_RISCV_CPU));
info->q_typename = g_strdup(typename);
+ dyn_class = object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU);
+ info->q_static = dyn_class == NULL;
+
QAPI_LIST_PREPEND(*cpu_list, info);
}
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (84 preceding siblings ...)
2023-05-05 1:02 ` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-07 22:21 ` Alistair Francis
2023-05-05 1:02 ` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Alistair Francis
` (4 subsequent siblings)
90 siblings, 1 reply; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Bin Meng, Fei Wu, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis, LIU Zhiwei
From: Bin Meng <bmeng@tinylab.org>
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
Some comments are also added to indicate that predicate() must be
provided for an implemented CSR.
Reported-by: Fei Wu <fei2.wu@intel.com>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 865ee9efda..4451bd1263 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3826,6 +3826,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+ /* ensure CSR is implemented by checking predicate */
+ if (!csr_ops[csrno].predicate) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
/* privileged spec version check */
if (env->priv_ver < csr_min_priv) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -3843,7 +3848,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
* illegal instruction exception should be triggered instead of virtual
* instruction exception. Hence this comes after the read / write check.
*/
- g_assert(csr_ops[csrno].predicate != NULL);
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
@@ -4032,7 +4036,10 @@ static RISCVException write_jvt(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-/* Control and Status Register function table */
+/*
+ * Control and Status Register function table
+ * riscv_csr_operations::predicate() must be provided for an implemented CSR
+ */
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 87/89] target/riscv: Fix Guest Physical Address Translation
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (85 preceding siblings ...)
2023-05-05 1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Alistair Francis
` (3 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Irina Ryapolova, Weiwei Li, Alistair Francis
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
Before changing the flow check for sv39/48/57.
According to specification (for Supervisor mode):
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
pages.
Instruction fetch addresses and load and store effective addresses, which are
64 bits,
must have bits 63–39 all equal to bit 38, or else a page-fault exception will
occur.
Likewise for Sv48 and Sv57.
So the high bits are equal to bit 38 for sv39.
According to specification (for Hypervisor mode):
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault
exception occurs.
For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault
exception occurs.
For example we are trying to access address 0xffff_ffff_ff01_0000 with only
G-translation enabled.
So expected behavior is to generate exception. But qemu doesn't generate such
exception.
For the old check, we get
va_bits == 41, mask == (1 << 24) - 1, masked_msbs == (0xffff_ffff_ff01_0000 >>
40) & mask == mask.
Accordingly, the condition masked_msbs != 0 && masked_msbs != mask is not
fulfilled
and the check passes.
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 32a65f8007..b68dcfe7b6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -837,17 +837,24 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
- target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
- } else {
- mask = 0;
- }
- masked_msbs = (addr >> (va_bits - 1)) & mask;
+ if (first_stage == true) {
+ target_ulong mask, masked_msbs;
- if (masked_msbs != 0 && masked_msbs != mask) {
- return TRANSLATE_FAIL;
+ if (TARGET_LONG_BITS > (va_bits - 1)) {
+ mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ } else {
+ mask = 0;
+ }
+ masked_msbs = (addr >> (va_bits - 1)) & mask;
+
+ if (masked_msbs != 0 && masked_msbs != mask) {
+ return TRANSLATE_FAIL;
+ }
+ } else {
+ if (vm != VM_1_10_SV32 && addr >> va_bits != 0) {
+ return TRANSLATE_FAIL;
+ }
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (86 preceding siblings ...)
2023-05-05 1:02 ` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:02 ` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Alistair Francis
` (2 subsequent siblings)
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alexandre Ghiti, Andrea Parri, Alistair Francis
From: Alexandre Ghiti <alexghiti@rivosinc.com>
As per the specification, in 64-bit, if any of the pte reserved bits
60-54 is set an exception should be triggered (see 4.4.1, "Addressing and
Memory Protection"). In addition, we must check the napot/pbmt bits are
not set if those extensions are not active.
Reported-by: Andrea Parri <andrea@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fb63b8e125..59f0ffd9e1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -644,6 +644,7 @@ typedef enum {
#define PTE_SOFT 0x300 /* Reserved for Software */
#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
+#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b68dcfe7b6..57d04385f1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -927,13 +927,20 @@ restart:
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
- } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
- ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
- ppn = pte >> PTE_PPN_SHIFT;
- if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
+ if (pte & PTE_RESERVED) {
+ return TRANSLATE_FAIL;
+ }
+
+ if (!pbmte && (pte & PTE_PBMT)) {
return TRANSLATE_FAIL;
}
+
+ if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
+ return TRANSLATE_FAIL;
+ }
+
+ ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
}
if (!(pte & PTE_V)) {
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (87 preceding siblings ...)
2023-05-05 1:02 ` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Alistair Francis
@ 2023-05-05 1:02 ` Alistair Francis
2023-05-05 1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 15:00 ` Richard Henderson
90 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:02 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Rahul Pathak, Mayuresh Chitale,
Daniel Henrique Barboza, Alistair Francis
From: Rahul Pathak <rpathak@ventanamicro.com>
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and general information can be found here:
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu_vendorid.h | 4 ++++
target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b29090ad86..04af50983e 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -41,6 +41,7 @@
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
+#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
index a5aa249bc9..96b6b9c2cb 100644
--- a/target/riscv/cpu_vendorid.h
+++ b/target/riscv/cpu_vendorid.h
@@ -3,4 +3,8 @@
#define THEAD_VENDOR_ID 0x5b7
+#define VEYRON_V1_MARCHID 0x8000000000010000
+#define VEYRON_V1_MIMPID 0x111
+#define VEYRON_V1_MVENDORID 0x61f
+
#endif /* TARGET_RISCV_CPU_VENDORID_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index befa64528f..db0875fb43 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -422,6 +422,43 @@ static void rv64_thead_c906_cpu_init(Object *obj)
#endif
}
+static void rv64_veyron_v1_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+ env->priv_ver = PRIV_VERSION_1_12_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu = true;
+ cpu->cfg.ext_icbom = true;
+ cpu->cfg.cbom_blocksize = 64;
+ cpu->cfg.cboz_blocksize = 64;
+ cpu->cfg.ext_icboz = true;
+ cpu->cfg.ext_smaia = true;
+ cpu->cfg.ext_ssaia = true;
+ cpu->cfg.ext_sscofpmf = true;
+ cpu->cfg.ext_sstc = true;
+ cpu->cfg.ext_svinval = true;
+ cpu->cfg.ext_svnapot = true;
+ cpu->cfg.ext_svpbmt = true;
+ cpu->cfg.ext_smstateen = true;
+ cpu->cfg.ext_zba = true;
+ cpu->cfg.ext_zbb = true;
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zbs = true;
+ cpu->cfg.ext_XVentanaCondOps = true;
+
+ cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
+ cpu->cfg.marchid = VEYRON_V1_MARCHID;
+ cpu->cfg.mimpid = VEYRON_V1_MIMPID;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV48);
+#endif
+}
+
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
@@ -1827,6 +1864,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
--
2.40.0
^ permalink raw reply related [flat|nested] 97+ messages in thread
* Re: [PULL 00/89] riscv-to-apply queue
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (88 preceding siblings ...)
2023-05-05 1:02 ` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Alistair Francis
@ 2023-05-05 1:05 ` Alistair Francis
2023-05-05 1:08 ` Alistair Francis
2023-05-05 15:00 ` Richard Henderson
90 siblings, 1 reply; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
On Fri, May 5, 2023 at 11:03 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
>
> Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
>
> for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
>
> target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
In an abundance of caution this has been signed with a new key after a
recent security incident.
I don't believe anything happened to the old one, but just in case I
have created a new one. Let me know if there is anything you would
like me to do to verify the new key. Then I will revoke the old one.
Alistair
>
> ----------------------------------------------------------------
> First RISC-V PR for 8.1
>
> * CPURISCVState related cleanup and simplification
> * Refactor Zicond and reuse in XVentanaCondOps
> * Fix invalid riscv,event-to-mhpmcounters entry
> * Support subsets of code size reduction extension
> * Fix itrigger when icount is used
> * Simplification for RVH related check and code style fix
> * Add signature dump function for spike to run ACT tests
> * Rework MISA writing
> * Fix mstatus.MPP related support
> * Use check for relationship between Zdinx/Zhinx{min} and Zfinx
> * Fix the H extension TVM trap
> * A large collection of mstatus sum changes and cleanups
> * Zero init APLIC internal state
> * Implement query-cpu-definitions
> * Restore the predicate() NULL check behavior
> * Fix Guest Physical Address Translation
> * Make sure an exception is raised if a pte is malformed
> * Add Ventana's Veyron V1 CPU
>
> ----------------------------------------------------------------
> Alexandre Ghiti (1):
> riscv: Make sure an exception is raised if a pte is malformed
>
> Bin Meng (1):
> target/riscv: Restore the predicate() NULL check behavior
>
> Conor Dooley (1):
> target/riscv: fix invalid riscv,event-to-mhpmcounters entry
>
> Daniel Henrique Barboza (23):
> target/riscv: sync env->misa_ext* with cpu->cfg in realize()
> target/riscv: remove MISA properties from isa_edata_arr[]
> target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
> target/riscv: introduce riscv_cpu_add_misa_properties()
> target/riscv: remove cpu->cfg.ext_a
> target/riscv: remove cpu->cfg.ext_c
> target/riscv: remove cpu->cfg.ext_d
> target/riscv: remove cpu->cfg.ext_f
> target/riscv: remove cpu->cfg.ext_i
> target/riscv: remove cpu->cfg.ext_e
> target/riscv: remove cpu->cfg.ext_m
> target/riscv: remove cpu->cfg.ext_s
> target/riscv: remove cpu->cfg.ext_u
> target/riscv: remove cpu->cfg.ext_h
> target/riscv: remove cpu->cfg.ext_j
> target/riscv: remove cpu->cfg.ext_v
> target/riscv: remove riscv_cpu_sync_misa_cfg()
> target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
> target/riscv: add RVG and remove cpu->cfg.ext_g
> target/riscv/cpu.c: redesign register_cpu_props()
> target/riscv: add CPU QOM header
> target/riscv: add query-cpy-definitions support
> target/riscv: add TYPE_RISCV_DYNAMIC_CPU
>
> Fei Wu (2):
> target/riscv: Separate priv from mmu_idx
> target/riscv: Reduce overhead of MSTATUS_SUM change
>
> Irina Ryapolova (1):
> target/riscv: Fix Guest Physical Address Translation
>
> Ivan Klokov (1):
> hw/intc/riscv_aplic: Zero init APLIC internal state
>
> LIU Zhiwei (7):
> target/riscv: Fix priv version dependency for vector and zfh
> target/riscv: Fix itrigger when icount is used
> target/riscv: Convert env->virt to a bool env->virt_enabled
> target/riscv: Extract virt enabled state from tb flags
> target/riscv: Add a general status enum for extensions
> target/riscv: Encode the FS and VS on a normal way for tb flags
> target/riscv: Add a tb flags field for vstart
>
> Philipp Tomsich (2):
> target/riscv: refactor Zicond support
> target/riscv: redirect XVentanaCondOps to use the Zicond functions
>
> Rahul Pathak (1):
> target/riscv: add Ventana's Veyron V1 CPU
>
> Richard Henderson (18):
> target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
> target/riscv: Use cpu_ld*_code_mmu for HLVX
> target/riscv: Handle HLV, HSV via helpers
> target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
> target/riscv: Introduce mmuidx_sum
> target/riscv: Introduce mmuidx_priv
> target/riscv: Introduce mmuidx_2stage
> target/riscv: Move hstatus.spvp check to check_access_hlsv
> target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
> target/riscv: Check SUM in the correct register
> target/riscv: Hoist second stage mode change to callers
> target/riscv: Hoist pbmte and hade out of the level loop
> target/riscv: Move leaf pte processing out of level loop
> target/riscv: Suppress pte update with is_debug
> target/riscv: Don't modify SUM with is_debug
> target/riscv: Merge checks for reserved pte flags
> target/riscv: Reorg access check in get_physical_address
> target/riscv: Reorg sum check in get_physical_address
>
> Weiwei Li (30):
> target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
> target/riscv: Simplify getting RISCVCPU pointer from env
> target/riscv: Simplify type conversion for CPURISCVState
> target/riscv: Simplify arguments for riscv_csrrw_check
> target/riscv: add cfg properties for Zc* extension
> target/riscv: add support for Zca extension
> target/riscv: add support for Zcf extension
> target/riscv: add support for Zcd extension
> target/riscv: add support for Zcb extension
> target/riscv: add support for Zcmp extension
> target/riscv: add support for Zcmt extension
> target/riscv: expose properties for Zc* extension
> disas/riscv.c: add disasm support for Zc*
> target/riscv: Add support for Zce
> target/riscv: Remove redundant call to riscv_cpu_virt_enabled
> target/riscv: Remove redundant check on RVH
> target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
> target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
> target/riscv: Remove redundant parentheses
> target/riscv: Fix addr type for get_physical_address
> target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
> target/riscv: Remove riscv_cpu_virt_enabled()
> target/riscv: Fix format for indentation
> target/riscv: Fix format for comments
> target/riscv: Fix lines with over 80 characters
> hw/riscv: Add signature dump function for spike to run ACT tests
> target/riscv: Fix the mstatus.MPP value after executing MRET
> target/riscv: Use PRV_RESERVED instead of PRV_H
> target/riscv: Legalize MPP value in write_mstatus
> target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
>
> Yi Chen (1):
> target/riscv: fix H extension TVM trap
>
> MAINTAINERS | 2 +-
> qapi/machine-target.json | 6 +-
> include/hw/char/riscv_htif.h | 3 +
> target/riscv/cpu-qom.h | 71 +++
> target/riscv/cpu.h | 155 ++---
> target/riscv/cpu_bits.h | 27 +-
> target/riscv/cpu_vendorid.h | 4 +
> target/riscv/helper.h | 15 +-
> target/riscv/internals.h | 35 ++
> target/riscv/pmp.h | 9 +-
> target/riscv/sbi_ecall_interface.h | 8 +-
> target/riscv/time_helper.h | 2 +-
> target/riscv/insn16.decode | 62 +-
> disas/riscv.c | 228 ++++++-
> hw/char/riscv_htif.c | 44 +-
> hw/intc/riscv_aplic.c | 2 +-
> hw/riscv/spike.c | 13 +
> target/riscv/arch_dump.c | 7 +-
> target/riscv/cpu.c | 571 +++++++++++-------
> target/riscv/cpu_helper.c | 671 +++++++++++----------
> target/riscv/csr.c | 331 +++++-----
> target/riscv/debug.c | 21 +-
> target/riscv/fpu_helper.c | 24 +-
> target/riscv/gdbstub.c | 9 +-
> target/riscv/m128_helper.c | 16 +-
> target/riscv/machine.c | 43 +-
> target/riscv/op_helper.c | 147 ++++-
> target/riscv/pmp.c | 66 +-
> target/riscv/pmu.c | 23 +-
> target/riscv/riscv-qmp-cmds.c | 57 ++
> target/riscv/time_helper.c | 15 +-
> target/riscv/translate.c | 109 ++--
> target/riscv/vector_helper.c | 317 +++++-----
> target/riscv/zce_helper.c | 55 ++
> target/riscv/insn_trans/trans_privileged.c.inc | 8 +-
> target/riscv/insn_trans/trans_rvd.c.inc | 18 +
> target/riscv/insn_trans/trans_rvf.c.inc | 20 +-
> target/riscv/insn_trans/trans_rvh.c.inc | 127 ++--
> target/riscv/insn_trans/trans_rvi.c.inc | 4 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 58 +-
> target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++
> target/riscv/insn_trans/trans_rvzicond.c.inc | 36 +-
> target/riscv/insn_trans/trans_xthead.c.inc | 14 +-
> .../riscv/insn_trans/trans_xventanacondops.c.inc | 18 +-
> target/riscv/meson.build | 6 +-
> 45 files changed, 2488 insertions(+), 1300 deletions(-)
> create mode 100644 target/riscv/cpu-qom.h
> create mode 100644 target/riscv/riscv-qmp-cmds.c
> create mode 100644 target/riscv/zce_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 00/89] riscv-to-apply queue
2023-05-05 1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
@ 2023-05-05 1:08 ` Alistair Francis
0 siblings, 0 replies; 97+ messages in thread
From: Alistair Francis @ 2023-05-05 1:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
On Fri, May 5, 2023 at 11:05 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Fri, May 5, 2023 at 11:03 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
> >
> > Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100)
> >
> > are available in the Git repository at:
> >
> > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
> >
> > for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
> >
> > target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
>
> In an abundance of caution this has been signed with a new key after a
> recent security incident.
>
> I don't believe anything happened to the old one, but just in case I
> have created a new one. Let me know if there is anything you would
> like me to do to verify the new key. Then I will revoke the old one.
I forgot to add, the new one is here:
https://keyserver.ubuntu.com/pks/lookup?search=AF7C95130C538013&fingerprint=on&op=index
it should propagate through
Alistair
>
> Alistair
>
> >
> > ----------------------------------------------------------------
> > First RISC-V PR for 8.1
> >
> > * CPURISCVState related cleanup and simplification
> > * Refactor Zicond and reuse in XVentanaCondOps
> > * Fix invalid riscv,event-to-mhpmcounters entry
> > * Support subsets of code size reduction extension
> > * Fix itrigger when icount is used
> > * Simplification for RVH related check and code style fix
> > * Add signature dump function for spike to run ACT tests
> > * Rework MISA writing
> > * Fix mstatus.MPP related support
> > * Use check for relationship between Zdinx/Zhinx{min} and Zfinx
> > * Fix the H extension TVM trap
> > * A large collection of mstatus sum changes and cleanups
> > * Zero init APLIC internal state
> > * Implement query-cpu-definitions
> > * Restore the predicate() NULL check behavior
> > * Fix Guest Physical Address Translation
> > * Make sure an exception is raised if a pte is malformed
> > * Add Ventana's Veyron V1 CPU
> >
> > ----------------------------------------------------------------
> > Alexandre Ghiti (1):
> > riscv: Make sure an exception is raised if a pte is malformed
> >
> > Bin Meng (1):
> > target/riscv: Restore the predicate() NULL check behavior
> >
> > Conor Dooley (1):
> > target/riscv: fix invalid riscv,event-to-mhpmcounters entry
> >
> > Daniel Henrique Barboza (23):
> > target/riscv: sync env->misa_ext* with cpu->cfg in realize()
> > target/riscv: remove MISA properties from isa_edata_arr[]
> > target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
> > target/riscv: introduce riscv_cpu_add_misa_properties()
> > target/riscv: remove cpu->cfg.ext_a
> > target/riscv: remove cpu->cfg.ext_c
> > target/riscv: remove cpu->cfg.ext_d
> > target/riscv: remove cpu->cfg.ext_f
> > target/riscv: remove cpu->cfg.ext_i
> > target/riscv: remove cpu->cfg.ext_e
> > target/riscv: remove cpu->cfg.ext_m
> > target/riscv: remove cpu->cfg.ext_s
> > target/riscv: remove cpu->cfg.ext_u
> > target/riscv: remove cpu->cfg.ext_h
> > target/riscv: remove cpu->cfg.ext_j
> > target/riscv: remove cpu->cfg.ext_v
> > target/riscv: remove riscv_cpu_sync_misa_cfg()
> > target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
> > target/riscv: add RVG and remove cpu->cfg.ext_g
> > target/riscv/cpu.c: redesign register_cpu_props()
> > target/riscv: add CPU QOM header
> > target/riscv: add query-cpy-definitions support
> > target/riscv: add TYPE_RISCV_DYNAMIC_CPU
> >
> > Fei Wu (2):
> > target/riscv: Separate priv from mmu_idx
> > target/riscv: Reduce overhead of MSTATUS_SUM change
> >
> > Irina Ryapolova (1):
> > target/riscv: Fix Guest Physical Address Translation
> >
> > Ivan Klokov (1):
> > hw/intc/riscv_aplic: Zero init APLIC internal state
> >
> > LIU Zhiwei (7):
> > target/riscv: Fix priv version dependency for vector and zfh
> > target/riscv: Fix itrigger when icount is used
> > target/riscv: Convert env->virt to a bool env->virt_enabled
> > target/riscv: Extract virt enabled state from tb flags
> > target/riscv: Add a general status enum for extensions
> > target/riscv: Encode the FS and VS on a normal way for tb flags
> > target/riscv: Add a tb flags field for vstart
> >
> > Philipp Tomsich (2):
> > target/riscv: refactor Zicond support
> > target/riscv: redirect XVentanaCondOps to use the Zicond functions
> >
> > Rahul Pathak (1):
> > target/riscv: add Ventana's Veyron V1 CPU
> >
> > Richard Henderson (18):
> > target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
> > target/riscv: Use cpu_ld*_code_mmu for HLVX
> > target/riscv: Handle HLV, HSV via helpers
> > target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
> > target/riscv: Introduce mmuidx_sum
> > target/riscv: Introduce mmuidx_priv
> > target/riscv: Introduce mmuidx_2stage
> > target/riscv: Move hstatus.spvp check to check_access_hlsv
> > target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
> > target/riscv: Check SUM in the correct register
> > target/riscv: Hoist second stage mode change to callers
> > target/riscv: Hoist pbmte and hade out of the level loop
> > target/riscv: Move leaf pte processing out of level loop
> > target/riscv: Suppress pte update with is_debug
> > target/riscv: Don't modify SUM with is_debug
> > target/riscv: Merge checks for reserved pte flags
> > target/riscv: Reorg access check in get_physical_address
> > target/riscv: Reorg sum check in get_physical_address
> >
> > Weiwei Li (30):
> > target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
> > target/riscv: Simplify getting RISCVCPU pointer from env
> > target/riscv: Simplify type conversion for CPURISCVState
> > target/riscv: Simplify arguments for riscv_csrrw_check
> > target/riscv: add cfg properties for Zc* extension
> > target/riscv: add support for Zca extension
> > target/riscv: add support for Zcf extension
> > target/riscv: add support for Zcd extension
> > target/riscv: add support for Zcb extension
> > target/riscv: add support for Zcmp extension
> > target/riscv: add support for Zcmt extension
> > target/riscv: expose properties for Zc* extension
> > disas/riscv.c: add disasm support for Zc*
> > target/riscv: Add support for Zce
> > target/riscv: Remove redundant call to riscv_cpu_virt_enabled
> > target/riscv: Remove redundant check on RVH
> > target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
> > target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
> > target/riscv: Remove redundant parentheses
> > target/riscv: Fix addr type for get_physical_address
> > target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
> > target/riscv: Remove riscv_cpu_virt_enabled()
> > target/riscv: Fix format for indentation
> > target/riscv: Fix format for comments
> > target/riscv: Fix lines with over 80 characters
> > hw/riscv: Add signature dump function for spike to run ACT tests
> > target/riscv: Fix the mstatus.MPP value after executing MRET
> > target/riscv: Use PRV_RESERVED instead of PRV_H
> > target/riscv: Legalize MPP value in write_mstatus
> > target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
> >
> > Yi Chen (1):
> > target/riscv: fix H extension TVM trap
> >
> > MAINTAINERS | 2 +-
> > qapi/machine-target.json | 6 +-
> > include/hw/char/riscv_htif.h | 3 +
> > target/riscv/cpu-qom.h | 71 +++
> > target/riscv/cpu.h | 155 ++---
> > target/riscv/cpu_bits.h | 27 +-
> > target/riscv/cpu_vendorid.h | 4 +
> > target/riscv/helper.h | 15 +-
> > target/riscv/internals.h | 35 ++
> > target/riscv/pmp.h | 9 +-
> > target/riscv/sbi_ecall_interface.h | 8 +-
> > target/riscv/time_helper.h | 2 +-
> > target/riscv/insn16.decode | 62 +-
> > disas/riscv.c | 228 ++++++-
> > hw/char/riscv_htif.c | 44 +-
> > hw/intc/riscv_aplic.c | 2 +-
> > hw/riscv/spike.c | 13 +
> > target/riscv/arch_dump.c | 7 +-
> > target/riscv/cpu.c | 571 +++++++++++-------
> > target/riscv/cpu_helper.c | 671 +++++++++++----------
> > target/riscv/csr.c | 331 +++++-----
> > target/riscv/debug.c | 21 +-
> > target/riscv/fpu_helper.c | 24 +-
> > target/riscv/gdbstub.c | 9 +-
> > target/riscv/m128_helper.c | 16 +-
> > target/riscv/machine.c | 43 +-
> > target/riscv/op_helper.c | 147 ++++-
> > target/riscv/pmp.c | 66 +-
> > target/riscv/pmu.c | 23 +-
> > target/riscv/riscv-qmp-cmds.c | 57 ++
> > target/riscv/time_helper.c | 15 +-
> > target/riscv/translate.c | 109 ++--
> > target/riscv/vector_helper.c | 317 +++++-----
> > target/riscv/zce_helper.c | 55 ++
> > target/riscv/insn_trans/trans_privileged.c.inc | 8 +-
> > target/riscv/insn_trans/trans_rvd.c.inc | 18 +
> > target/riscv/insn_trans/trans_rvf.c.inc | 20 +-
> > target/riscv/insn_trans/trans_rvh.c.inc | 127 ++--
> > target/riscv/insn_trans/trans_rvi.c.inc | 4 +-
> > target/riscv/insn_trans/trans_rvv.c.inc | 58 +-
> > target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++
> > target/riscv/insn_trans/trans_rvzicond.c.inc | 36 +-
> > target/riscv/insn_trans/trans_xthead.c.inc | 14 +-
> > .../riscv/insn_trans/trans_xventanacondops.c.inc | 18 +-
> > target/riscv/meson.build | 6 +-
> > 45 files changed, 2488 insertions(+), 1300 deletions(-)
> > create mode 100644 target/riscv/cpu-qom.h
> > create mode 100644 target/riscv/riscv-qmp-cmds.c
> > create mode 100644 target/riscv/zce_helper.c
> > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 00/89] riscv-to-apply queue
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
` (89 preceding siblings ...)
2023-05-05 1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
@ 2023-05-05 15:00 ` Richard Henderson
90 siblings, 0 replies; 97+ messages in thread
From: Richard Henderson @ 2023-05-05 15:00 UTC (permalink / raw)
To: Alistair Francis, qemu-devel; +Cc: Alistair Francis
On 5/5/23 02:01, Alistair Francis wrote:
> The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
>
> Merge tag 'qga-pull-2023-05-04' ofhttps://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
>
> for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
>
> target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
>
> ----------------------------------------------------------------
> First RISC-V PR for 8.1
>
> * CPURISCVState related cleanup and simplification
> * Refactor Zicond and reuse in XVentanaCondOps
> * Fix invalid riscv,event-to-mhpmcounters entry
> * Support subsets of code size reduction extension
> * Fix itrigger when icount is used
> * Simplification for RVH related check and code style fix
> * Add signature dump function for spike to run ACT tests
> * Rework MISA writing
> * Fix mstatus.MPP related support
> * Use check for relationship between Zdinx/Zhinx{min} and Zfinx
> * Fix the H extension TVM trap
> * A large collection of mstatus sum changes and cleanups
> * Zero init APLIC internal state
> * Implement query-cpu-definitions
> * Restore the predicate() NULL check behavior
> * Fix Guest Physical Address Translation
> * Make sure an exception is raised if a pte is malformed
> * Add Ventana's Veyron V1 CPU
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior
2023-05-05 1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
@ 2023-05-07 22:21 ` Alistair Francis
2023-05-10 17:18 ` Michael Tokarev
0 siblings, 1 reply; 97+ messages in thread
From: Alistair Francis @ 2023-05-07 22:21 UTC (permalink / raw)
To: qemu-devel, qemu-stable
Cc: Bin Meng, Fei Wu, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis, LIU Zhiwei
On Fri, May 5, 2023 at 11:08 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> From: Bin Meng <bmeng@tinylab.org>
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
> Some comments are also added to indicate that predicate() must be
> provided for an implemented CSR.
>
> Reported-by: Fei Wu <fei2.wu@intel.com>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Sorry, I didn't realise I should have done this with the PR, but this
is a good candidate for going into 8.0.1
Alistair
> ---
> target/riscv/csr.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 865ee9efda..4451bd1263 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3826,6 +3826,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* ensure CSR is implemented by checking predicate */
> + if (!csr_ops[csrno].predicate) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> /* privileged spec version check */
> if (env->priv_ver < csr_min_priv) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -3843,7 +3848,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> * illegal instruction exception should be triggered instead of virtual
> * instruction exception. Hence this comes after the read / write check.
> */
> - g_assert(csr_ops[csrno].predicate != NULL);
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> @@ -4032,7 +4036,10 @@ static RISCVException write_jvt(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -/* Control and Status Register function table */
> +/*
> + * Control and Status Register function table
> + * riscv_csr_operations::predicate() must be provided for an implemented CSR
> + */
> riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* User Floating-Point CSRs */
> [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 19/89] target/riscv: Fix itrigger when icount is used
2023-05-05 1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
@ 2023-05-07 22:22 ` Alistair Francis
2023-05-10 17:17 ` Michael Tokarev
0 siblings, 1 reply; 97+ messages in thread
From: Alistair Francis @ 2023-05-07 22:22 UTC (permalink / raw)
To: qemu-devel, qemu-stable; +Cc: LIU Zhiwei, Weiwei Li, Alistair Francis
On Fri, May 5, 2023 at 11:04 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
> The reason is that when execute helper_mret or helper_sret, it will
> cause a call to icount_get_raw_locked (), which needs set can_do_io flag
> on cpustate.
>
> Thus we setting this flag when execute these two instructions.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This is also a good candidate for 8.0.1
Alistair
> ---
> target/riscv/insn_trans/trans_privileged.c.inc | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
> index 59501b2780..e3bee971c6 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -77,6 +77,9 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
> #ifndef CONFIG_USER_ONLY
> if (has_ext(ctx, RVS)) {
> decode_save_opc(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_sret(cpu_pc, cpu_env);
> exit_tb(ctx); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> @@ -93,6 +96,9 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
> {
> #ifndef CONFIG_USER_ONLY
> decode_save_opc(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_mret(cpu_pc, cpu_env);
> exit_tb(ctx); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 19/89] target/riscv: Fix itrigger when icount is used
2023-05-07 22:22 ` Alistair Francis
@ 2023-05-10 17:17 ` Michael Tokarev
0 siblings, 0 replies; 97+ messages in thread
From: Michael Tokarev @ 2023-05-10 17:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-stable
Cc: LIU Zhiwei, Weiwei Li, Alistair Francis
08.05.2023 01:22, Alistair Francis wrote:
> On Fri, May 5, 2023 at 11:04 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>>
>> When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
>> The reason is that when execute helper_mret or helper_sret, it will
>> cause a call to icount_get_raw_locked (), which needs set can_do_io flag
>> on cpustate.
>>
>> Thus we setting this flag when execute these two instructions.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>
> This is also a good candidate for 8.0.1
Queued for 8.0 (and for 7.2 if it will ever be). Thanks!
/mjt
^ permalink raw reply [flat|nested] 97+ messages in thread
* Re: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior
2023-05-07 22:21 ` Alistair Francis
@ 2023-05-10 17:18 ` Michael Tokarev
0 siblings, 0 replies; 97+ messages in thread
From: Michael Tokarev @ 2023-05-10 17:18 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-stable
Cc: Bin Meng, Fei Wu, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis, LIU Zhiwei
08.05.2023 01:21, Alistair Francis wrote:
> On Fri, May 5, 2023 at 11:08 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> From: Bin Meng <bmeng@tinylab.org>
>>
>> When reading a non-existent CSR QEMU should raise illegal instruction
>> exception, but currently it just exits due to the g_assert() check.
>>
>> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
>> Some comments are also added to indicate that predicate() must be
>> provided for an implemented CSR.
>>
>> Reported-by: Fei Wu <fei2.wu@intel.com>
>> Signed-off-by: Bin Meng <bmeng@tinylab.org>
>> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>> Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>
> Sorry, I didn't realise I should have done this with the PR, but this
> is a good candidate for going into 8.0.1
Queued for 8.0, with minor context tweak. Thank you!
/mjt
^ permalink raw reply [flat|nested] 97+ messages in thread
end of thread, other threads:[~2023-05-10 17:18 UTC | newest]
Thread overview: 97+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:01 ` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Alistair Francis
2023-05-05 1:01 ` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Alistair Francis
2023-05-05 1:01 ` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Alistair Francis
2023-05-05 1:01 ` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Alistair Francis
2023-05-05 1:01 ` [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check Alistair Francis
2023-05-05 1:01 ` [PULL 06/89] target/riscv: refactor Zicond support Alistair Francis
2023-05-05 1:01 ` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Alistair Francis
2023-05-05 1:01 ` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Alistair Francis
2023-05-05 1:01 ` [PULL 09/89] target/riscv: add cfg properties for Zc* extension Alistair Francis
2023-05-05 1:01 ` [PULL 10/89] target/riscv: add support for Zca extension Alistair Francis
2023-05-05 1:01 ` [PULL 11/89] target/riscv: add support for Zcf extension Alistair Francis
2023-05-05 1:01 ` [PULL 12/89] target/riscv: add support for Zcd extension Alistair Francis
2023-05-05 1:01 ` [PULL 13/89] target/riscv: add support for Zcb extension Alistair Francis
2023-05-05 1:01 ` [PULL 14/89] target/riscv: add support for Zcmp extension Alistair Francis
2023-05-05 1:01 ` [PULL 15/89] target/riscv: add support for Zcmt extension Alistair Francis
2023-05-05 1:01 ` [PULL 16/89] target/riscv: expose properties for Zc* extension Alistair Francis
2023-05-05 1:01 ` [PULL 17/89] disas/riscv.c: add disasm support for Zc* Alistair Francis
2023-05-05 1:01 ` [PULL 18/89] target/riscv: Add support for Zce Alistair Francis
2023-05-05 1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
2023-05-07 22:22 ` Alistair Francis
2023-05-10 17:17 ` Michael Tokarev
2023-05-05 1:01 ` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 21/89] target/riscv: Remove redundant check on RVH Alistair Francis
2023-05-05 1:01 ` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 25/89] target/riscv: Remove redundant parentheses Alistair Francis
2023-05-05 1:01 ` [PULL 26/89] target/riscv: Fix addr type for get_physical_address Alistair Francis
2023-05-05 1:01 ` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Alistair Francis
2023-05-05 1:01 ` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Alistair Francis
2023-05-05 1:01 ` [PULL 29/89] target/riscv: Fix format for indentation Alistair Francis
2023-05-05 1:01 ` [PULL 30/89] target/riscv: Fix format for comments Alistair Francis
2023-05-05 1:01 ` [PULL 31/89] target/riscv: Fix lines with over 80 characters Alistair Francis
2023-05-05 1:01 ` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests Alistair Francis
2023-05-05 1:01 ` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Alistair Francis
2023-05-05 1:01 ` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Alistair Francis
2023-05-05 1:01 ` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Alistair Francis
2023-05-05 1:01 ` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties() Alistair Francis
2023-05-05 1:01 ` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Alistair Francis
2023-05-05 1:01 ` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Alistair Francis
2023-05-05 1:01 ` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Alistair Francis
2023-05-05 1:01 ` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f Alistair Francis
2023-05-05 1:01 ` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Alistair Francis
2023-05-05 1:01 ` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Alistair Francis
2023-05-05 1:01 ` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Alistair Francis
2023-05-05 1:01 ` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Alistair Francis
2023-05-05 1:01 ` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Alistair Francis
2023-05-05 1:01 ` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Alistair Francis
2023-05-05 1:01 ` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Alistair Francis
2023-05-05 1:02 ` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Alistair Francis
2023-05-05 1:02 ` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Alistair Francis
2023-05-05 1:02 ` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Alistair Francis
2023-05-05 1:02 ` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Alistair Francis
2023-05-05 1:02 ` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Alistair Francis
2023-05-05 1:02 ` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Alistair Francis
2023-05-05 1:02 ` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Alistair Francis
2023-05-05 1:02 ` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Alistair Francis
2023-05-05 1:02 ` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Alistair Francis
2023-05-05 1:02 ` [PULL 57/89] target/riscv: fix H extension TVM trap Alistair Francis
2023-05-05 1:02 ` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Alistair Francis
2023-05-05 1:02 ` [PULL 59/89] target/riscv: Add a general status enum for extensions Alistair Francis
2023-05-05 1:02 ` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Alistair Francis
2023-05-05 1:02 ` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Alistair Francis
2023-05-05 1:02 ` [PULL 62/89] target/riscv: Add a tb flags field for vstart Alistair Francis
2023-05-05 1:02 ` [PULL 63/89] target/riscv: Separate priv from mmu_idx Alistair Francis
2023-05-05 1:02 ` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Alistair Francis
2023-05-05 1:02 ` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Alistair Francis
2023-05-05 1:02 ` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Alistair Francis
2023-05-05 1:02 ` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Alistair Francis
2023-05-05 1:02 ` [PULL 68/89] target/riscv: Introduce mmuidx_sum Alistair Francis
2023-05-05 1:02 ` [PULL 69/89] target/riscv: Introduce mmuidx_priv Alistair Francis
2023-05-05 1:02 ` [PULL 70/89] target/riscv: Introduce mmuidx_2stage Alistair Francis
2023-05-05 1:02 ` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Alistair Francis
2023-05-05 1:02 ` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Alistair Francis
2023-05-05 1:02 ` [PULL 73/89] target/riscv: Check SUM in the correct register Alistair Francis
2023-05-05 1:02 ` [PULL 74/89] target/riscv: Hoist second stage mode change to callers Alistair Francis
2023-05-05 1:02 ` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Alistair Francis
2023-05-05 1:02 ` [PULL 76/89] target/riscv: Move leaf pte processing out of " Alistair Francis
2023-05-05 1:02 ` [PULL 77/89] target/riscv: Suppress pte update with is_debug Alistair Francis
2023-05-05 1:02 ` [PULL 78/89] target/riscv: Don't modify SUM " Alistair Francis
2023-05-05 1:02 ` [PULL 79/89] target/riscv: Merge checks for reserved pte flags Alistair Francis
2023-05-05 1:02 ` [PULL 80/89] target/riscv: Reorg access check in get_physical_address Alistair Francis
2023-05-05 1:02 ` [PULL 81/89] target/riscv: Reorg sum " Alistair Francis
2023-05-05 1:02 ` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Alistair Francis
2023-05-05 1:02 ` [PULL 83/89] target/riscv: add CPU QOM header Alistair Francis
2023-05-05 1:02 ` [PULL 84/89] target/riscv: add query-cpy-definitions support Alistair Francis
2023-05-05 1:02 ` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Alistair Francis
2023-05-05 1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
2023-05-07 22:21 ` Alistair Francis
2023-05-10 17:18 ` Michael Tokarev
2023-05-05 1:02 ` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Alistair Francis
2023-05-05 1:02 ` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Alistair Francis
2023-05-05 1:02 ` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Alistair Francis
2023-05-05 1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:08 ` Alistair Francis
2023-05-05 15:00 ` Richard Henderson
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