From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 10/10] target/riscv/tcg: add hash table insert helpers
Date: Fri, 6 Oct 2023 10:21:34 -0300 [thread overview]
Message-ID: <20231006132134.1135297-11-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20231006132134.1135297-1-dbarboza@ventanamicro.com>
Latest patches added several g_hash_table_insert() patterns. Add two
helpers, one for each user hash, to make the code cleaner.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index d7540274f4..d4ad1c09b3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -42,12 +42,24 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
GUINT_TO_POINTER(ext_offset));
}
+static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value)
+{
+ g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset),
+ (gpointer)value);
+}
+
static bool cpu_misa_ext_is_user_set(uint32_t misa_bit)
{
return g_hash_table_contains(misa_ext_user_opts,
GUINT_TO_POINTER(misa_bit));
}
+static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value)
+{
+ g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit),
+ (gpointer)value);
+}
+
static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
bool enabled)
{
@@ -296,9 +308,7 @@ static void riscv_cpu_commit_profile(RISCVCPU *cpu, RISCVCPUProfile *profile)
continue;
}
- g_hash_table_insert(misa_ext_user_opts,
- GUINT_TO_POINTER(bit),
- (gpointer)profile->enabled);
+ cpu_misa_ext_add_user_opt(bit, profile->enabled);
riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
}
@@ -314,9 +324,8 @@ static void riscv_cpu_commit_profile(RISCVCPU *cpu, RISCVCPUProfile *profile)
continue;
}
- g_hash_table_insert(multi_ext_user_opts,
- GUINT_TO_POINTER(ext_offset),
- (gpointer)profile->enabled);
+ cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
+
isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
}
}
@@ -724,9 +733,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
return;
}
- g_hash_table_insert(misa_ext_user_opts,
- GUINT_TO_POINTER(misa_bit),
- (gpointer)value);
+ cpu_misa_ext_add_user_opt(misa_bit, value);
prev_val = env->misa_ext & misa_bit;
@@ -867,9 +874,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
return;
}
- g_hash_table_insert(multi_ext_user_opts,
- GUINT_TO_POINTER(multi_ext_cfg->offset),
- (gpointer)value);
+ cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value);
prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
--
2.41.0
next prev parent reply other threads:[~2023-10-06 13:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-06 13:21 [PATCH v2 00/10] riscv: RVA22U64 profile support Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag Daniel Henrique Barboza
2023-10-11 2:51 ` Alistair Francis
2023-10-12 18:23 ` Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 02/10] target/riscv/cpu.c: add zihpm " Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 03/10] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-11 2:54 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 04/10] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-11 2:55 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 05/10] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 06/10] target/riscv/tcg: commit profiles during realize() Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 07/10] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-11 3:03 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 08/10] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-11 3:04 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit Daniel Henrique Barboza
2023-10-06 13:21 ` Daniel Henrique Barboza [this message]
2023-10-11 3:01 ` [PATCH v2 00/10] riscv: RVA22U64 profile support Alistair Francis
2023-10-12 19:07 ` Daniel Henrique Barboza
2023-10-16 2:23 ` Alistair Francis
2023-10-16 9:03 ` Andrew Jones
2023-10-17 3:55 ` Alistair Francis
2023-10-17 8:08 ` Andrew Jones
2023-10-18 21:45 ` Daniel Henrique Barboza
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