From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v2 08/10] target/riscv/tcg: add riscv_cpu_write_misa_bit()
Date: Wed, 11 Oct 2023 13:04:11 +1000 [thread overview]
Message-ID: <CAKmqyKMEsEUcYvJUowE7ycjW+ZF4geD2JpndEVGnj6P9LAL7mA@mail.gmail.com> (raw)
In-Reply-To: <20231006132134.1135297-9-dbarboza@ventanamicro.com>
On Sat, Oct 7, 2023 at 12:29 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We have two instances of the setting/clearing a MISA bit from
> env->misa_ext and env->misa_ext_mask pattern. And the next patch will
> end up adding one more.
>
> Create a helper to avoid code repetition.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 44 ++++++++++++++++++++------------------
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 58de4428a9..b1e778913c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> GUINT_TO_POINTER(ext_offset));
> }
>
> +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
> + bool enabled)
> +{
> + CPURISCVState *env = &cpu->env;
> +
> + if (enabled) {
> + env->misa_ext |= bit;
> + env->misa_ext_mask |= bit;
> + } else {
> + env->misa_ext &= ~bit;
> + env->misa_ext_mask &= ~bit;
> + }
> +}
> +
> static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> @@ -700,20 +714,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> return;
> }
>
> - if (value) {
> - if (!generic_cpu) {
> - g_autofree char *cpuname = riscv_cpu_get_name(cpu);
> - error_setg(errp, "'%s' CPU does not allow enabling extensions",
> - cpuname);
> - return;
> - }
> -
> - env->misa_ext |= misa_bit;
> - env->misa_ext_mask |= misa_bit;
> - } else {
> - env->misa_ext &= ~misa_bit;
> - env->misa_ext_mask &= ~misa_bit;
> + if (value && !generic_cpu) {
> + g_autofree char *cpuname = riscv_cpu_get_name(cpu);
> + error_setg(errp, "'%s' CPU does not allow enabling extensions",
> + cpuname);
> + return;
> }
> +
> + riscv_cpu_write_misa_bit(cpu, misa_bit, value);
> }
>
> static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> @@ -757,7 +765,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> */
> static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> {
> - CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
> bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
> int i;
>
> @@ -778,13 +785,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> NULL, (void *)misa_cfg);
> object_property_set_description(cpu_obj, name, desc);
> if (use_def_vals) {
> - if (misa_cfg->enabled) {
> - env->misa_ext |= bit;
> - env->misa_ext_mask |= bit;
> - } else {
> - env->misa_ext &= ~bit;
> - env->misa_ext_mask &= ~bit;
> - }
> + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit,
> + misa_cfg->enabled);
> }
> }
> }
> --
> 2.41.0
>
>
next prev parent reply other threads:[~2023-10-11 3:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-06 13:21 [PATCH v2 00/10] riscv: RVA22U64 profile support Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag Daniel Henrique Barboza
2023-10-11 2:51 ` Alistair Francis
2023-10-12 18:23 ` Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 02/10] target/riscv/cpu.c: add zihpm " Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 03/10] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-11 2:54 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 04/10] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-11 2:55 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 05/10] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 06/10] target/riscv/tcg: commit profiles during realize() Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 07/10] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-11 3:03 ` Alistair Francis
2023-10-06 13:21 ` [PATCH v2 08/10] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-11 3:04 ` Alistair Francis [this message]
2023-10-06 13:21 ` [PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit Daniel Henrique Barboza
2023-10-06 13:21 ` [PATCH v2 10/10] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-11 3:01 ` [PATCH v2 00/10] riscv: RVA22U64 profile support Alistair Francis
2023-10-12 19:07 ` Daniel Henrique Barboza
2023-10-16 2:23 ` Alistair Francis
2023-10-16 9:03 ` Andrew Jones
2023-10-17 3:55 ` Alistair Francis
2023-10-17 8:08 ` Andrew Jones
2023-10-18 21:45 ` Daniel Henrique Barboza
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