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From: Alvin Chang via <qemu-devel@nongnu.org>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>
Cc: <alistair.francis@wdc.com>, <bin.meng@windriver.com>,
	<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
	<zhiwei_liu@linux.alibaba.com>,
	Alvin Chang <alvinga@andestech.com>
Subject: [PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec
Date: Fri, 16 Feb 2024 14:13:28 +0800	[thread overview]
Message-ID: <20240216061332.50229-1-alvinga@andestech.com> (raw)

The RISC-V Debug specification defines CSR "tcontrol" in the trigger
module:
  https://github.com/riscv/riscv-debug-spec

This series implements it and the related operations.

Alvin Chang (4):
  target/riscv: Add CSR tcontrol of debug trigger module
  target/riscv: Reset CSR tcontrol when the trigger module resets
  target/riscv: Set the value of CSR tcontrol when trapping to M-mode
  target/riscv: Set the value of CSR tcontrol when mret is executed

 target/riscv/cpu.h        |  1 +
 target/riscv/cpu_bits.h   |  3 +++
 target/riscv/cpu_helper.c |  6 ++++++
 target/riscv/csr.c        | 15 +++++++++++++++
 target/riscv/debug.c      |  1 +
 target/riscv/op_helper.c  |  6 ++++++
 6 files changed, 32 insertions(+)

-- 
2.34.1



             reply	other threads:[~2024-02-16  6:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-16  6:13 Alvin Chang via [this message]
2024-02-16  6:13 ` [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module Alvin Chang via
2024-02-16 12:51   ` Daniel Henrique Barboza
2024-02-16 13:42     ` Alvin Che-Chia Chang(張哲嘉)
2024-02-16 15:04       ` Daniel Henrique Barboza
2024-02-16 15:05   ` Daniel Henrique Barboza
2024-02-16  6:13 ` [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets Alvin Chang via
2024-02-16 13:22   ` Daniel Henrique Barboza
2024-02-16  6:13 ` [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode Alvin Chang via
2024-02-16 13:22   ` Daniel Henrique Barboza
2024-02-16  6:13 ` [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed Alvin Chang via
2024-02-16 13:23   ` Daniel Henrique Barboza

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