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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Alvin Chang <alvinga@andestech.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets
Date: Fri, 16 Feb 2024 10:22:08 -0300	[thread overview]
Message-ID: <4428f5b0-b2fb-4520-9e8f-b17ba09fd076@ventanamicro.com> (raw)
In-Reply-To: <20240216061332.50229-3-alvinga@andestech.com>



On 2/16/24 03:13, Alvin Chang wrote:
> When the trigger module resets, reset the value of CSR tcontrol as zero.
> 
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/debug.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index e30d99cc2f..e3832a643e 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -941,5 +941,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
>           timer_del(env->itrigger_timer[i]);
>       }
>   
> +    env->tcontrol = 0;
>       env->mcontext = 0;
>   }


  reply	other threads:[~2024-02-16 13:23 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-16  6:13 [PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec Alvin Chang via
2024-02-16  6:13 ` [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module Alvin Chang via
2024-02-16 12:51   ` Daniel Henrique Barboza
2024-02-16 13:42     ` Alvin Che-Chia Chang(張哲嘉)
2024-02-16 15:04       ` Daniel Henrique Barboza
2024-02-16 15:05   ` Daniel Henrique Barboza
2024-02-16  6:13 ` [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets Alvin Chang via
2024-02-16 13:22   ` Daniel Henrique Barboza [this message]
2024-02-16  6:13 ` [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode Alvin Chang via
2024-02-16 13:22   ` Daniel Henrique Barboza
2024-02-16  6:13 ` [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed Alvin Chang via
2024-02-16 13:23   ` Daniel Henrique Barboza

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