From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Alvin Chang <alvinga@andestech.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed
Date: Fri, 16 Feb 2024 10:23:12 -0300 [thread overview]
Message-ID: <6c3d27c6-82f4-49f7-b074-73d04274c1b7@ventanamicro.com> (raw)
In-Reply-To: <20240216061332.50229-5-alvinga@andestech.com>
On 2/16/24 03:13, Alvin Chang wrote:
> The RISC-V debug specification defines the following operation for CSR
> tcontrol when "mret" is executed:
> - tcontrol.MTE is set to the value of tcontrol.MPTE
>
> This commit implements the above operation into helper_mret().
>
> Note that from tech-debug mailing list:
> https://lists.riscv.org/g/tech-debug/topic/102702615#1461
> The debug specification does not mention the operation to tcontrol.MPTE
> when "mret" is executed. Therefore, we just keep its current value.
>
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/op_helper.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index f414aaebdb..12822b3afa 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -347,6 +347,12 @@ target_ulong helper_mret(CPURISCVState *env)
> mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> }
> env->mstatus = mstatus;
> +
> + uint64_t tcontrol = env->tcontrol;
> + tcontrol = set_field(tcontrol, TCONTROL_MTE,
> + get_field(tcontrol, TCONTROL_MPTE));
> + env->tcontrol = tcontrol;
> +
> riscv_cpu_set_mode(env, prev_priv);
>
> if (riscv_has_ext(env, RVH)) {
prev parent reply other threads:[~2024-02-16 13:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 6:13 [PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec Alvin Chang via
2024-02-16 6:13 ` [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module Alvin Chang via
2024-02-16 12:51 ` Daniel Henrique Barboza
2024-02-16 13:42 ` Alvin Che-Chia Chang(張哲嘉)
2024-02-16 15:04 ` Daniel Henrique Barboza
2024-02-16 15:05 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets Alvin Chang via
2024-02-16 13:22 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode Alvin Chang via
2024-02-16 13:22 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed Alvin Chang via
2024-02-16 13:23 ` Daniel Henrique Barboza [this message]
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