From: Alvin Chang via <qemu-devel@nongnu.org>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>
Cc: <alistair.francis@wdc.com>, <bin.meng@windriver.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>,
Alvin Chang <alvinga@andestech.com>
Subject: [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module
Date: Fri, 16 Feb 2024 14:13:29 +0800 [thread overview]
Message-ID: <20240216061332.50229-2-alvinga@andestech.com> (raw)
In-Reply-To: <20240216061332.50229-1-alvinga@andestech.com>
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 15 +++++++++++++++
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f52dce78ba..f9ae3e3025 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -364,6 +364,7 @@ struct CPUArchState {
target_ulong tdata1[RV_MAX_TRIGGERS];
target_ulong tdata2[RV_MAX_TRIGGERS];
target_ulong tdata3[RV_MAX_TRIGGERS];
+ target_ulong tcontrol;
target_ulong mcontext;
struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fc2068ee4d..3b3a7a0fa4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -353,6 +353,7 @@
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
#define CSR_TINFO 0x7a4
+#define CSR_TCONTROL 0x7a5
#define CSR_MCONTEXT 0x7a8
/* Debug Mode Registers */
@@ -900,6 +901,8 @@ typedef enum RISCVException {
#define JVT_BASE (~0x3F)
/* Debug Sdtrig CSR masks */
+#define TCONTROL_MTE BIT(3)
+#define TCONTROL_MPTE BIT(7)
#define MCONTEXT32 0x0000003F
#define MCONTEXT64 0x0000000000001FFFULL
#define MCONTEXT32_HCONTEXT 0x0000007F
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4e8ac13b9..816c530481 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3937,6 +3937,20 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_tcontrol(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->tcontrol;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tcontrol(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ env->tcontrol = val & (TCONTROL_MPTE | TCONTROL_MTE);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mcontext(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -4861,6 +4875,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
+ [CSR_TCONTROL] = { "tcontrol", debug, read_tcontrol, write_tcontrol },
[CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext },
/* User Pointer Masking */
--
2.34.1
next prev parent reply other threads:[~2024-02-16 6:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 6:13 [PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec Alvin Chang via
2024-02-16 6:13 ` Alvin Chang via [this message]
2024-02-16 12:51 ` [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module Daniel Henrique Barboza
2024-02-16 13:42 ` Alvin Che-Chia Chang(張哲嘉)
2024-02-16 15:04 ` Daniel Henrique Barboza
2024-02-16 15:05 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets Alvin Chang via
2024-02-16 13:22 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode Alvin Chang via
2024-02-16 13:22 ` Daniel Henrique Barboza
2024-02-16 6:13 ` [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed Alvin Chang via
2024-02-16 13:23 ` Daniel Henrique Barboza
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