[PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

[PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

[Jason Chien]

This patch series adds the support for Zve32x and Zvx64x and makes vector
registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.

Jason Chien (5):
  target/riscv: Add support for Zve32x extension
  target/riscv: Expose Zve32x extension to users
  target/riscv: Add support for Zve64x extension
  target/riscv: Expose Zve64x extension to users
  target/riscv: Relax vector register check in RISCV gdbstub

 target/riscv/cpu.c                      |  4 +++
 target/riscv/cpu_cfg.h                  |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/gdbstub.c                  |  2 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
 target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
 7 files changed, 30 insertions(+), 19 deletions(-)

-- 
2.43.2

[PATCH 1/5] target/riscv: Add support for Zve32x extension

[Jason Chien]

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                      |  1 +
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 6 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fd0c7efdda..10ccae3323 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index be39870691..beb3d10213 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -90,6 +90,7 @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c994a72634..ebbe56d9a2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 726096444f..d96feea5d3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab434..f00f1ee886 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ab6db817db..ce539528e6 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
-- 
2.43.2

[PATCH 2/5] target/riscv: Expose Zve32x extension to users

[Jason Chien]

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 10ccae3323..37e4557b47 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1469,6 +1469,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
-- 
2.43.2

[PATCH 3/5] target/riscv: Add support for Zve64x extension

[Jason Chien]

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c         |  1 +
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 37e4557b47..8b5d1eb6a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -155,6 +155,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index beb3d10213..5d99856822 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -93,6 +93,7 @@ struct RISCVCPUConfig {
     bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
+    bool ext_zve64x;
     bool ext_zvbb;
     bool ext_zvbc;
     bool ext_zvkb;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ce539528e6..d630879286 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -488,17 +488,22 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 
     /* The Zve64d extension depends on the Zve64f extension */
     if (cpu->cfg.ext_zve64d) {
+        if (!riscv_has_ext(env, RVD)) {
+            error_setg(errp, "Zve64d/V extensions require D extension");
+            return;
+        }
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
     }
 
-    /* The Zve64f extension depends on the Zve32f extension */
+    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
     if (cpu->cfg.ext_zve64f) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
     }
 
-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-        error_setg(errp, "Zve64d/V extensions require D extension");
-        return;
+    /* The Zve64x extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve64x) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     /* The Zve32f extension depends on the Zve32x extension */
@@ -665,10 +670,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
+    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
         error_setg(
             errp,
-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
+            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
         return;
     }
 
-- 
2.43.2

[PATCH 4/5] target/riscv: Expose Zve64x extension to users

[Jason Chien]

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8b5d1eb6a8..58b2a94694 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1473,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 
     MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
-- 
2.43.2

[PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub

[Jason Chien]

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ca9b71f7bb..f30de083e9 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -323,7 +323,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  32, "riscv-32bit-fpu.xml", 0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         int base_reg = cs->gdb_num_regs;
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
-- 
2.43.2

Re: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

[Jason Chien]

[-- Attachment #1: Type: text/plain, Size: 1055 bytes --]

Ping. Can anyone review the patches please?

Jason Chien <jason.chien@sifive.com> 於 2024年3月7日 週四 上午1:09寫道：

> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> Jason Chien (5):
>   target/riscv: Add support for Zve32x extension
>   target/riscv: Expose Zve32x extension to users
>   target/riscv: Add support for Zve64x extension
>   target/riscv: Expose Zve64x extension to users
>   target/riscv: Relax vector register check in RISCV gdbstub
>
>  target/riscv/cpu.c                      |  4 +++
>  target/riscv/cpu_cfg.h                  |  2 ++
>  target/riscv/cpu_helper.c               |  2 +-
>  target/riscv/csr.c                      |  2 +-
>  target/riscv/gdbstub.c                  |  2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
>  target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
>  7 files changed, 30 insertions(+), 19 deletions(-)
>
> --
> 2.43.2
>
>

[-- Attachment #2: Type: text/html, Size: 1453 bytes --]

Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

[Jason Chien]

[-- Attachment #1: Type: text/plain, Size: 5393 bytes --]

Ping. Can anyone review the patches please?

Jason Chien <jason.chien@sifive.com> 於 2024年3月7日 週四 上午1:09寫道：

> Add support for Zve32x extension and replace some checks for Zve32f with
> Zve32x, since Zve32f depends on Zve32x.
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> ---
>  target/riscv/cpu.c                      |  1 +
>  target/riscv/cpu_cfg.h                  |  1 +
>  target/riscv/cpu_helper.c               |  2 +-
>  target/riscv/csr.c                      |  2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
>  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
>  6 files changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fd0c7efdda..10ccae3323 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
>      ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
>      ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
> +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
>      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
>      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
>      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index be39870691..beb3d10213 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -90,6 +90,7 @@ struct RISCVCPUConfig {
>      bool ext_zhinx;
>      bool ext_zhinxmin;
>      bool ext_zve32f;
> +    bool ext_zve32x;
>      bool ext_zve64f;
>      bool ext_zve64d;
>      bool ext_zvbb;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index c994a72634..ebbe56d9a2 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
>      *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
>      *cs_base = 0;
>
> -    if (cpu->cfg.ext_zve32f) {
> +    if (cpu->cfg.ext_zve32x) {
>          /*
>           * If env->vl equals to VLMAX, we can use generic vector operation
>           * expanders (GVEC) to accerlate the vector operations.
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 726096444f..d96feea5d3 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
>  static RISCVException vs(CPURISCVState *env, int csrno)
>  {
> -    if (riscv_cpu_cfg(env)->ext_zve32f) {
> +    if (riscv_cpu_cfg(env)->ext_zve32x) {
>  #if !defined(CONFIG_USER_ONLY)
>          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>              return RISCV_EXCP_ILLEGAL_INST;
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9e101ab434..f00f1ee886 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int
> rs1, TCGv s2)
>  {
>      TCGv s1, dst;
>
> -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
>          return false;
>      }
>
> @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv
> s1, TCGv s2)
>  {
>      TCGv dst;
>
> -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
>          return false;
>      }
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index ab6db817db..ce539528e6 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
>          return;
>      }
>
> -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
> -        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
> -        return;
> +    /* The Zve32f extension depends on the Zve32x extension */
> +    if (cpu->cfg.ext_zve32f) {
> +        if (!riscv_has_ext(env, RVF)) {
> +            error_setg(errp, "Zve32f/Zve64f extensions require F
> extension");
> +            return;
> +        }
> +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
>      }
>
>      if (cpu->cfg.ext_zvfh) {
> @@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
>          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
>      }
>
> -    /*
> -     * In principle Zve*x would also suffice here, were they supported
> -     * in qemu
> -     */
>      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
>           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
> cpu->cfg.ext_zvksed ||
> -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
> +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
>          error_setg(errp,
>                     "Vector crypto extensions require V or Zve*
> extensions");
>          return;
> --
> 2.43.2
>
>

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Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

[Daniel Henrique Barboza]

Hi Jason,

Care to re-send please? The patches don't apply to neither riscv-to-apply.next
nor master.


Thanks,

Daniel

On 3/19/24 13:23, Jason Chien wrote:
> Ping. Can anyone review the patches please?
> 
> Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>> 於 2024年3月7日 週四 上午1:09寫道：
> 
>     Add support for Zve32x extension and replace some checks for Zve32f with
>     Zve32x, since Zve32f depends on Zve32x.
> 
>     Signed-off-by: Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>>
>     Reviewed-by: Frank Chang <frank.chang@sifive.com <mailto:frank.chang@sifive.com>>
>     Reviewed-by: Max Chou <max.chou@sifive.com <mailto:max.chou@sifive.com>>
>     ---
>       target/riscv/cpu.c                      |  1 +
>       target/riscv/cpu_cfg.h                  |  1 +
>       target/riscv/cpu_helper.c               |  2 +-
>       target/riscv/csr.c                      |  2 +-
>       target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
>       target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
>       6 files changed, 14 insertions(+), 12 deletions(-)
> 
>     diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>     index fd0c7efdda..10ccae3323 100644
>     --- a/target/riscv/cpu.c
>     +++ b/target/riscv/cpu.c
>     @@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>           ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
>           ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
>           ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
>     +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
>           ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
>           ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
>           ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
>     diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>     index be39870691..beb3d10213 100644
>     --- a/target/riscv/cpu_cfg.h
>     +++ b/target/riscv/cpu_cfg.h
>     @@ -90,6 +90,7 @@ struct RISCVCPUConfig {
>           bool ext_zhinx;
>           bool ext_zhinxmin;
>           bool ext_zve32f;
>     +    bool ext_zve32x;
>           bool ext_zve64f;
>           bool ext_zve64d;
>           bool ext_zvbb;
>     diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>     index c994a72634..ebbe56d9a2 100644
>     --- a/target/riscv/cpu_helper.c
>     +++ b/target/riscv/cpu_helper.c
>     @@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
>           *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
>           *cs_base = 0;
> 
>     -    if (cpu->cfg.ext_zve32f) {
>     +    if (cpu->cfg.ext_zve32x) {
>               /*
>                * If env->vl equals to VLMAX, we can use generic vector operation
>                * expanders (GVEC) to accerlate the vector operations.
>     diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>     index 726096444f..d96feea5d3 100644
>     --- a/target/riscv/csr.c
>     +++ b/target/riscv/csr.c
>     @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> 
>       static RISCVException vs(CPURISCVState *env, int csrno)
>       {
>     -    if (riscv_cpu_cfg(env)->ext_zve32f) {
>     +    if (riscv_cpu_cfg(env)->ext_zve32x) {
>       #if !defined(CONFIG_USER_ONLY)
>               if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>                   return RISCV_EXCP_ILLEGAL_INST;
>     diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
>     index 9e101ab434..f00f1ee886 100644
>     --- a/target/riscv/insn_trans/trans_rvv.c.inc
>     +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>     @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>       {
>           TCGv s1, dst;
> 
>     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
>               return false;
>           }
> 
>     @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
>       {
>           TCGv dst;
> 
>     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
>               return false;
>           }
> 
>     diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
>     index ab6db817db..ce539528e6 100644
>     --- a/target/riscv/tcg/tcg-cpu.c
>     +++ b/target/riscv/tcg/tcg-cpu.c
>     @@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>               return;
>           }
> 
>     -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
>     -        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>     -        return;
>     +    /* The Zve32f extension depends on the Zve32x extension */
>     +    if (cpu->cfg.ext_zve32f) {
>     +        if (!riscv_has_ext(env, RVF)) {
>     +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>     +            return;
>     +        }
>     +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
>           }
> 
>           if (cpu->cfg.ext_zvfh) {
>     @@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>               cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
>           }
> 
>     -    /*
>     -     * In principle Zve*x would also suffice here, were they supported
>     -     * in qemu
>     -     */
>           if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
>                cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
>     -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
>     +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
>               error_setg(errp,
>                          "Vector crypto extensions require V or Zve* extensions");
>               return;
>     -- 
>     2.43.2
> 

Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

[Jason Chien]

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I will re-send shortly. Thanks.

Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年3月20日 週三
上午5:19寫道：

> Hi Jason,
>
> Care to re-send please? The patches don't apply to neither
> riscv-to-apply.next
> nor master.
>
>
> Thanks,
>
> Daniel
>
> On 3/19/24 13:23, Jason Chien wrote:
> > Ping. Can anyone review the patches please?
> >
> > Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>> 於
> 2024年3月7日 週四 上午1:09寫道：
> >
> >     Add support for Zve32x extension and replace some checks for Zve32f
> with
> >     Zve32x, since Zve32f depends on Zve32x.
> >
> >     Signed-off-by: Jason Chien <jason.chien@sifive.com <mailto:
> jason.chien@sifive.com>>
> >     Reviewed-by: Frank Chang <frank.chang@sifive.com <mailto:
> frank.chang@sifive.com>>
> >     Reviewed-by: Max Chou <max.chou@sifive.com <mailto:
> max.chou@sifive.com>>
> >     ---
> >       target/riscv/cpu.c                      |  1 +
> >       target/riscv/cpu_cfg.h                  |  1 +
> >       target/riscv/cpu_helper.c               |  2 +-
> >       target/riscv/csr.c                      |  2 +-
> >       target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
> >       target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
> >       6 files changed, 14 insertions(+), 12 deletions(-)
> >
> >     diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >     index fd0c7efdda..10ccae3323 100644
> >     --- a/target/riscv/cpu.c
> >     +++ b/target/riscv/cpu.c
> >     @@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> >           ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
> >           ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
> >           ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
> >     +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
> >           ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
> >           ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
> >           ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0,
> ext_zvfbfmin),
> >     diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> >     index be39870691..beb3d10213 100644
> >     --- a/target/riscv/cpu_cfg.h
> >     +++ b/target/riscv/cpu_cfg.h
> >     @@ -90,6 +90,7 @@ struct RISCVCPUConfig {
> >           bool ext_zhinx;
> >           bool ext_zhinxmin;
> >           bool ext_zve32f;
> >     +    bool ext_zve32x;
> >           bool ext_zve64f;
> >           bool ext_zve64d;
> >           bool ext_zvbb;
> >     diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >     index c994a72634..ebbe56d9a2 100644
> >     --- a/target/riscv/cpu_helper.c
> >     +++ b/target/riscv/cpu_helper.c
> >     @@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> vaddr *pc,
> >           *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> >           *cs_base = 0;
> >
> >     -    if (cpu->cfg.ext_zve32f) {
> >     +    if (cpu->cfg.ext_zve32x) {
> >               /*
> >                * If env->vl equals to VLMAX, we can use generic vector
> operation
> >                * expanders (GVEC) to accerlate the vector operations.
> >     diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >     index 726096444f..d96feea5d3 100644
> >     --- a/target/riscv/csr.c
> >     +++ b/target/riscv/csr.c
> >     @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int
> csrno)
> >
> >       static RISCVException vs(CPURISCVState *env, int csrno)
> >       {
> >     -    if (riscv_cpu_cfg(env)->ext_zve32f) {
> >     +    if (riscv_cpu_cfg(env)->ext_zve32x) {
> >       #if !defined(CONFIG_USER_ONLY)
> >               if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> >                   return RISCV_EXCP_ILLEGAL_INST;
> >     diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> >     index 9e101ab434..f00f1ee886 100644
> >     --- a/target/riscv/insn_trans/trans_rvv.c.inc
> >     +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> >     @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd,
> int rs1, TCGv s2)
> >       {
> >           TCGv s1, dst;
> >
> >     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> >     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
> >               return false;
> >           }
> >
> >     @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd,
> TCGv s1, TCGv s2)
> >       {
> >           TCGv dst;
> >
> >     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> >     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
> >               return false;
> >           }
> >
> >     diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> >     index ab6db817db..ce539528e6 100644
> >     --- a/target/riscv/tcg/tcg-cpu.c
> >     +++ b/target/riscv/tcg/tcg-cpu.c
> >     @@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU
> *cpu, Error **errp)
> >               return;
> >           }
> >
> >     -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
> >     -        error_setg(errp, "Zve32f/Zve64f extensions require F
> extension");
> >     -        return;
> >     +    /* The Zve32f extension depends on the Zve32x extension */
> >     +    if (cpu->cfg.ext_zve32f) {
> >     +        if (!riscv_has_ext(env, RVF)) {
> >     +            error_setg(errp, "Zve32f/Zve64f extensions require F
> extension");
> >     +            return;
> >     +        }
> >     +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x),
> true);
> >           }
> >
> >           if (cpu->cfg.ext_zvfh) {
> >     @@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU
> *cpu, Error **errp)
> >               cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc),
> true);
> >           }
> >
> >     -    /*
> >     -     * In principle Zve*x would also suffice here, were they
> supported
> >     -     * in qemu
> >     -     */
> >           if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb ||
> cpu->cfg.ext_zvkg ||
> >                cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
> cpu->cfg.ext_zvksed ||
> >     -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
> >     +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
> >               error_setg(errp,
> >                          "Vector crypto extensions require V or Zve*
> extensions");
> >               return;
> >     --
> >     2.43.2
> >
>

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Re: [PATCH 4/5] target/riscv: Expose Zve64x extension to users

[Daniel Henrique Barboza]

On 3/6/24 14:08, Jason Chien wrote:
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> ---

Please add the following tag in this commit msg:


Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107


The link is a feature request named "target/riscv: zve32x/zve64x are not supported"
that was opened a couple of months ago. Adding this tag will close the bug (since by
this time we'll have both zve32x and zve64x) as soon as the series is merged to
master.


Thanks,


Daniel

>   target/riscv/cpu.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8b5d1eb6a8..58b2a94694 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1473,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>       MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
>       MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
>       MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
> +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
>       MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
>   
>       MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),