From: Chander Kashyap <chander.kashyap@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org,
kgene.kim@samsung.com, t.figa@samsung.com,
s.nawrocki@samsung.com, thomas.ab@samsung.com,
Chander Kashyap <chander.kashyap@linaro.org>
Subject: [PATCH 03/13] ARM: dts: fork out common Exynos5 nodes
Date: Thu, 6 Jun 2013 16:31:17 +0530 [thread overview]
Message-ID: <1370516488-25860-3-git-send-email-chander.kashyap@linaro.org> (raw)
In-Reply-To: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org>
In preparation of adding support for Exynos5420, which has many peripherals
similar to Exynos5250, a new common Exynos5 device tree source file is
created out of the existing Exynos5250 device tree source file. Only the
common nodes required for basic boot up on Exynos5420 based boards are moved
into this new file and the rest of the common nodes would be moved subsequently.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
arch/arm/boot/dts/exynos5.dtsi | 121 +++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 74 +----------------------
2 files changed, 122 insertions(+), 73 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos5.dtsi
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 0000000..ab56608
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,121 @@
+/*
+ * Samsung's Exynos5 SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos5 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ gic:interrupt-controller@10481000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ combiner:interrupt-controller@10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ samsung,combiner-nr = <32>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ };
+
+ watchdog {
+ compatible = "samsung,s3c2410-wdt";
+ reg = <0x101D0000 0x100>;
+ interrupts = <0 42 0>;
+ clock-names = "watchdog";
+ status = "disabled";
+ };
+
+ rtc {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x101E0000 0x100>;
+ interrupts = <0 43 0>, <0 44 0>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ serial@12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 52 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 53 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C30000 0x100>;
+ interrupts = <0 54 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ dwmmc_0: dwmmc0@12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_1: dwmmc1@12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_2: dwmmc2@12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4bd9e9c..e571d3b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,12 +17,11 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+/include/ "exynos5.dtsi"
/include/ "exynos5250-pinctrl.dtsi"
/ {
compatible = "samsung,exynos5250";
- interrupt-parent = <&gic>;
aliases {
spi0 = &spi_0;
@@ -51,11 +50,6 @@
pinctrl3 = &pinctrl_3;
};
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
-
pd_gsc: gsc-power-domain@0x10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -72,17 +66,6 @@
#clock-cells = <1>;
};
- gic:interrupt-controller@10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
@@ -91,22 +74,6 @@
<1 10 0xf08>;
};
- combiner:interrupt-controller@10440000 {
- compatible = "samsung,exynos4210-combiner";
- #interrupt-cells = <2>;
- interrupt-controller;
- samsung,combiner-nr = <32>;
- reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
- };
-
mct@101C0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
@@ -168,11 +135,7 @@
};
watchdog {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
clocks = <&clock 336>;
- clock-names = "watchdog";
};
codec@11000000 {
@@ -183,12 +146,8 @@
};
rtc {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
clocks = <&clock 337>;
clock-names = "rtc";
- status = "disabled";
};
tmu@10060000 {
@@ -200,35 +159,19 @@
};
serial@12C00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
clocks = <&clock 289>, <&clock 146>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C10000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
clocks = <&clock 290>, <&clock 147>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
clocks = <&clock 291>, <&clock 148>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C30000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
clocks = <&clock 292>, <&clock 149>;
- clock-names = "uart", "clk_uart_baud0";
};
sata@122F0000 {
@@ -405,33 +348,18 @@
};
dwmmc_0: dwmmc0@12200000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 280>, <&clock 139>;
- clock-names = "biu", "ciu";
};
dwmmc_1: dwmmc1@12210000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 281>, <&clock 140>;
- clock-names = "biu", "ciu";
};
dwmmc_2: dwmmc2@12220000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 282>, <&clock 141>;
- clock-names = "biu", "ciu";
};
dwmmc_3: dwmmc3@12230000 {
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: chander.kashyap@linaro.org (Chander Kashyap)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/13] ARM: dts: fork out common Exynos5 nodes
Date: Thu, 6 Jun 2013 16:31:17 +0530 [thread overview]
Message-ID: <1370516488-25860-3-git-send-email-chander.kashyap@linaro.org> (raw)
In-Reply-To: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org>
In preparation of adding support for Exynos5420, which has many peripherals
similar to Exynos5250, a new common Exynos5 device tree source file is
created out of the existing Exynos5250 device tree source file. Only the
common nodes required for basic boot up on Exynos5420 based boards are moved
into this new file and the rest of the common nodes would be moved subsequently.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
arch/arm/boot/dts/exynos5.dtsi | 121 +++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 74 +----------------------
2 files changed, 122 insertions(+), 73 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos5.dtsi
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 0000000..ab56608
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,121 @@
+/*
+ * Samsung's Exynos5 SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos5 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chipid at 10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ gic:interrupt-controller at 10481000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ combiner:interrupt-controller at 10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ samsung,combiner-nr = <32>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ };
+
+ watchdog {
+ compatible = "samsung,s3c2410-wdt";
+ reg = <0x101D0000 0x100>;
+ interrupts = <0 42 0>;
+ clock-names = "watchdog";
+ status = "disabled";
+ };
+
+ rtc {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x101E0000 0x100>;
+ interrupts = <0 43 0>, <0 44 0>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ serial at 12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 52 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 53 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C30000 0x100>;
+ interrupts = <0 54 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ dwmmc_0: dwmmc0 at 12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_1: dwmmc1 at 12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_2: dwmmc2 at 12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4bd9e9c..e571d3b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,12 +17,11 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+/include/ "exynos5.dtsi"
/include/ "exynos5250-pinctrl.dtsi"
/ {
compatible = "samsung,exynos5250";
- interrupt-parent = <&gic>;
aliases {
spi0 = &spi_0;
@@ -51,11 +50,6 @@
pinctrl3 = &pinctrl_3;
};
- chipid at 10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
-
pd_gsc: gsc-power-domain at 0x10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -72,17 +66,6 @@
#clock-cells = <1>;
};
- gic:interrupt-controller at 10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
@@ -91,22 +74,6 @@
<1 10 0xf08>;
};
- combiner:interrupt-controller at 10440000 {
- compatible = "samsung,exynos4210-combiner";
- #interrupt-cells = <2>;
- interrupt-controller;
- samsung,combiner-nr = <32>;
- reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
- };
-
mct at 101C0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
@@ -168,11 +135,7 @@
};
watchdog {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
clocks = <&clock 336>;
- clock-names = "watchdog";
};
codec at 11000000 {
@@ -183,12 +146,8 @@
};
rtc {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
clocks = <&clock 337>;
clock-names = "rtc";
- status = "disabled";
};
tmu at 10060000 {
@@ -200,35 +159,19 @@
};
serial at 12C00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
clocks = <&clock 289>, <&clock 146>;
- clock-names = "uart", "clk_uart_baud0";
};
serial at 12C10000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
clocks = <&clock 290>, <&clock 147>;
- clock-names = "uart", "clk_uart_baud0";
};
serial at 12C20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
clocks = <&clock 291>, <&clock 148>;
- clock-names = "uart", "clk_uart_baud0";
};
serial at 12C30000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
clocks = <&clock 292>, <&clock 149>;
- clock-names = "uart", "clk_uart_baud0";
};
sata at 122F0000 {
@@ -405,33 +348,18 @@
};
dwmmc_0: dwmmc0 at 12200000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 280>, <&clock 139>;
- clock-names = "biu", "ciu";
};
dwmmc_1: dwmmc1 at 12210000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 281>, <&clock 140>;
- clock-names = "biu", "ciu";
};
dwmmc_2: dwmmc2 at 12220000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 282>, <&clock 141>;
- clock-names = "biu", "ciu";
};
dwmmc_3: dwmmc3 at 12230000 {
--
1.7.9.5
next prev parent reply other threads:[~2013-06-06 11:02 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-06 11:01 [PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 02/13] ARM: Exynos: fix secondary cpu power control register address calculation Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-08 11:05 ` Tomasz Figa
2013-06-08 11:05 ` Tomasz Figa
2013-06-11 13:46 ` Chander Kashyap
2013-06-11 13:46 ` Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap [this message]
2013-06-06 11:01 ` [PATCH 03/13] ARM: dts: fork out common Exynos5 nodes Chander Kashyap
2013-06-06 11:14 ` Sachin Kamat
2013-06-06 11:14 ` Sachin Kamat
2013-06-08 11:12 ` Tomasz Figa
2013-06-08 11:12 ` Tomasz Figa
2013-06-11 13:49 ` Chander Kashyap
2013-06-11 13:49 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 04/13] ARM: dts: list the CPU nodes for Exynos5250 Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 16:54 ` Mark Rutland
2013-06-06 16:54 ` Mark Rutland
2013-06-10 9:18 ` Chander Kashyap
2013-06-10 9:18 ` Chander Kashyap
2013-06-08 11:16 ` Tomasz Figa
2013-06-08 11:16 ` Tomasz Figa
2013-06-10 9:18 ` Chander Kashyap
2013-06-10 9:18 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 05/13] ARM: Exynos: Add support for Exynos5420 SoC Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 06/13] serial: samsung: add support for Exynos5420 Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:35 ` Girish KS
2013-06-06 11:35 ` Girish KS
2013-06-10 9:05 ` Chander Kashyap
2013-06-10 9:05 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 07/13] ARM: Exynos: use four additional chipid bits to identify Exynos family Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 08/13] irqchip: exynos-combiner: set irq base as 256 for Exynos5420 Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-08 11:24 ` Tomasz Figa
2013-06-08 11:24 ` Tomasz Figa
2013-06-06 11:01 ` [PATCH 09/13] clk: exynos5420: register clocks using common clock framework Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-08 11:25 ` Tomasz Figa
2013-06-08 11:25 ` Tomasz Figa
2013-06-11 13:22 ` Chander Kashyap
2013-06-11 13:22 ` Chander Kashyap
2013-06-10 11:12 ` sunil joshi
2013-06-10 11:12 ` sunil joshi
2013-06-11 13:23 ` Chander Kashyap
2013-06-11 13:23 ` Chander Kashyap
2013-06-12 21:17 ` Tomasz Figa
2013-06-12 21:17 ` Tomasz Figa
2013-06-12 21:32 ` Andrew Bresticker
2013-06-12 21:32 ` Andrew Bresticker
2013-06-13 5:18 ` Chander Kashyap
2013-06-13 5:18 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 10/13] ARM: dts: Add initial device tree support for Exynos5420 Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 16:34 ` Mark Rutland
2013-06-06 16:34 ` Mark Rutland
2013-06-11 13:35 ` Chander Kashyap
2013-06-11 13:35 ` Chander Kashyap
2013-06-11 14:11 ` Mark Rutland
2013-06-11 14:11 ` Mark Rutland
2013-06-12 5:35 ` Subash Patel
2013-06-12 5:35 ` Subash Patel
2013-06-08 11:38 ` Tomasz Figa
2013-06-08 11:38 ` Tomasz Figa
2013-06-14 13:54 ` Chander Kashyap
2013-06-14 13:54 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 00/10] ARM: Exynos: Add Exynos5420 SoC support Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 01/10] ARM: dts: fork out common Exynos5 nodes Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 02/10] ARM: dts: list the CPU nodes for Exynos5250 Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 03/10] ARM: Exynos: Add support for Exynos5420 SoC Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 04/10] serial: samsung: select Exynos specific driver data if ARCH_EXYNOS is defined Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 05/10] ARM: Exynos: use four additional chipid bits to identify Exynos family Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 06/10] clk: exynos5420: register clocks using common clock framework Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 17:26 ` Andrew Bresticker
2013-06-14 17:26 ` Andrew Bresticker
2013-06-17 8:46 ` Chander Kashyap
2013-06-17 8:46 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 07/10] ARM: dts: Add initial device tree support for Exynos5420 Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-17 8:46 ` Mark Rutland
2013-06-17 8:46 ` Mark Rutland
[not found] ` <CAGOxZ51H_dtZN3Nx-=qU+gjHAEwgPA--SZrdiu-sBCANhdKtAw@mail.gmail.com>
2013-06-17 11:08 ` Chander Kashyap
2013-06-17 11:08 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 08/10] clocksource: exynos_mct: use (request/free)_irq calls for local timer registration Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-17 10:01 ` Mark Rutland
2013-06-17 10:01 ` Mark Rutland
2013-06-17 10:29 ` Chander Kashyap
2013-06-17 10:29 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 09/10] ARM: Exynos: add secondary CPU boot base location for Exynos5420 Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-14 14:02 ` [PATCH v2 10/10] ARM: Exynos: extend soft-reset support " Chander Kashyap
2013-06-14 14:02 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 11/13] clocksource: exynos_mct: extend local timer support for four cores Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 16:50 ` Mark Rutland
2013-06-06 16:50 ` Mark Rutland
2013-06-08 11:39 ` Tomasz Figa
2013-06-08 11:39 ` Tomasz Figa
2013-06-11 13:26 ` Chander Kashyap
2013-06-11 13:26 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 12/13] ARM: Exynos: add secondary CPU boot base location for Exynos5420 Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 13/13] ARM: Exynos: extend soft-reset support " Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-06 11:44 ` Tushar Behera
2013-06-06 11:44 ` Tushar Behera
2013-06-10 8:54 ` Kukjin Kim
2013-06-10 8:54 ` Kukjin Kim
2013-06-11 13:24 ` Chander Kashyap
2013-06-11 13:24 ` Chander Kashyap
2013-06-06 11:01 ` [PATCH 00/13] add exynos5420 support Chander Kashyap
2013-06-06 11:01 ` Chander Kashyap
2013-06-08 10:57 ` [PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs Tomasz Figa
2013-06-08 10:57 ` Tomasz Figa
2013-06-11 23:58 ` Olof Johansson
2013-06-11 23:58 ` Olof Johansson
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