From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH 02/16] drm/i915: add CRC #defines for ilk/snb
Date: Wed, 16 Oct 2013 22:55:47 +0200 [thread overview]
Message-ID: <1381956961-16875-3-git-send-email-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <1381956961-16875-1-git-send-email-daniel.vetter@ffwll.ch>
Also add a new _PIPE_INC macro which takes an base plus increment.
Much less likely to botch the job by missing an s/A/B/ somewhere.
v2: They've moved the bitfield. Argh!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++++++++++++++++----------
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d01eaf..984bf9e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
@@ -1844,19 +1845,31 @@
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
-#define _PIPE_CRC_RES_1_A_IVB (dev_priv->info->display_mmio_offset + 0x60064)
-#define _PIPE_CRC_RES_2_A_IVB (dev_priv->info->display_mmio_offset + 0x60068)
-#define _PIPE_CRC_RES_3_A_IVB (dev_priv->info->display_mmio_offset + 0x6006c)
-#define _PIPE_CRC_RES_4_A_IVB (dev_priv->info->display_mmio_offset + 0x60070)
-#define _PIPE_CRC_RES_5_A_IVB (dev_priv->info->display_mmio_offset + 0x60074)
+#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
+#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
+#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
+/* embedded DP port on the north display block, reserved on ivb */
+#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
+#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
+#define _PIPE_CRC_RES_1_A_IVB 0x60064
+#define _PIPE_CRC_RES_2_A_IVB 0x60068
+#define _PIPE_CRC_RES_3_A_IVB 0x6006c
+#define _PIPE_CRC_RES_4_A_IVB 0x60070
+#define _PIPE_CRC_RES_5_A_IVB 0x60074
+
+#define _PIPE_CRC_RES_RED_A_ILK 0x60060
+#define _PIPE_CRC_RES_GREEN_A_ILK 0x60064
+#define _PIPE_CRC_RES_BLUE_A_ILK 0x60068
+#define _PIPE_CRC_RES_RES1_A_ILK 0x6006c
+#define _PIPE_CRC_RES_RES2_A_ILK 0x60080
/* Pipe B CRC regs */
-#define _PIPE_CRC_CTL_B (dev_priv->info->display_mmio_offset + 0x61050)
-#define _PIPE_CRC_RES_1_B_IVB (dev_priv->info->display_mmio_offset + 0x61064)
-#define _PIPE_CRC_RES_2_B_IVB (dev_priv->info->display_mmio_offset + 0x61068)
-#define _PIPE_CRC_RES_3_B_IVB (dev_priv->info->display_mmio_offset + 0x6106c)
-#define _PIPE_CRC_RES_4_B_IVB (dev_priv->info->display_mmio_offset + 0x61070)
-#define _PIPE_CRC_RES_5_B_IVB (dev_priv->info->display_mmio_offset + 0x61074)
+#define _PIPE_CRC_CTL_B 0x61050
+#define _PIPE_CRC_RES_1_B_IVB 0x61064
+#define _PIPE_CRC_RES_2_B_IVB 0x61068
+#define _PIPE_CRC_RES_3_B_IVB 0x6106c
+#define _PIPE_CRC_RES_4_B_IVB 0x61070
+#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_CTL(pipe) _PIPE(pipe, _PIPE_CRC_CTL_A, _PIPE_CRC_CTL_B)
#define PIPE_CRC_RES_1_IVB(pipe) \
@@ -1870,6 +1883,17 @@
#define PIPE_CRC_RES_5_IVB(pipe) \
_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
+#define PIPE_CRC_RES_RED_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A_ILK, 0x01000)
+#define PIPE_CRC_RES_GREEN_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A_ILK, 0x01000)
+#define PIPE_CRC_RES_BLUE_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A_ILK, 0x01000)
+#define PIPE_CRC_RES_RES1_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_ILK, 0x01000)
+#define PIPE_CRC_RES_RES2_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_ILK, 0x01000)
+
/* Pipe A timing regs */
#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
--
1.8.4.rc3
next prev parent reply other threads:[~2013-10-16 21:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
2013-10-16 20:55 ` [PATCH 01/16] drm/i915: extract display_pipe_crc_update Daniel Vetter
2013-10-16 20:55 ` Daniel Vetter [this message]
2013-10-16 20:55 ` [PATCH 03/16] drm/i915: wire up CRC interrupt for ilk/snb Daniel Vetter
2013-10-16 20:55 ` [PATCH 04/16] drm/i915: use ->get_vblank_counter for the crc frame counter Daniel Vetter
2013-10-16 20:55 ` [PATCH 05/16] drm/i915: wait one vblank when disabling CRCs Daniel Vetter
2013-10-16 20:55 ` [PATCH 06/16] drm/i915: fix CRC debugfs setup Daniel Vetter
2013-10-16 20:55 ` [PATCH 07/16] drm/i915: crc support for hsw Daniel Vetter
2013-10-17 10:53 ` Damien Lespiau
2013-10-17 13:06 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 08/16] drm/i915: Adjust CRC capture for pre-gen5/vlv Daniel Vetter
2013-10-16 20:55 ` [PATCH 09/16] drm/i915: CRC source selection #defines for gmch/vlv chips Daniel Vetter
2013-10-16 20:55 ` [PATCH 10/16] drm/i915: Wire up CRC interrupts for pre-gen5/vlv Daniel Vetter
2013-10-16 20:55 ` [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv Daniel Vetter
2013-10-21 10:49 ` Ville Syrjälä
2013-10-21 15:13 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv Daniel Vetter
2013-10-21 10:50 ` Ville Syrjälä
2013-10-21 15:15 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 13/16] drm/i915: Add new CRC sources Daniel Vetter
2013-10-16 20:55 ` [PATCH 14/16] drm/i915: Wire up CRC support for gen3/4 Daniel Vetter
2013-10-16 20:56 ` [PATCH 15/16] drm/i915: Wire up gen2 CRC support Daniel Vetter
2013-10-16 20:56 ` [PATCH 16/16] drm/i915: Wire up CRC for vlv Daniel Vetter
2013-10-18 14:37 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Daniel Vetter
2013-10-18 14:37 ` [PATCH 2/3] drm/i915: Wire up CRC for vlv Daniel Vetter
2013-10-18 14:37 ` [PATCH 3/3] drm/i915: bikeshed the pipe CRC irq functions a bit Daniel Vetter
2013-10-21 10:22 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Ville Syrjälä
2013-10-21 15:17 ` Daniel Vetter
2013-10-21 15:26 ` [PATCH] " Daniel Vetter
2013-10-21 16:16 ` Ville Syrjälä
2013-10-21 16:35 ` Daniel Vetter
2013-10-21 12:08 ` [PATCH 00/16] CRC support for non-ivb Ville Syrjälä
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