Re: [PATCH 1/3] drm/i915: Wire up gen2 CRC support

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 1/3] drm/i915: Wire up gen2 CRC support
Date: Mon, 21 Oct 2013 13:22:40 +0300	[thread overview]
Message-ID: <20131021102240.GS13047@intel.com> (raw)
In-Reply-To: <1382107027-20521-1-git-send-email-daniel.vetter@ffwll.ch>

On Fri, Oct 18, 2013 at 04:37:05PM +0200, Daniel Vetter wrote:
> Really simple, and we don't even have working frame numbers.
> 
> v2: Actually enable it ...
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e3f0980..3f4fd7c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
>  	return single_open(file, display_crc_ctl_show, dev);
>  }
>  
> +static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
> +				 uint32_t *val)
> +{
> +	switch (source) {
> +	case INTEL_PIPE_CRC_SOURCE_PIPE:
> +		*val = PIPE_CRC_ENABLE;

On gen3+ the border is always included in the crc. Maybe we should
always include it on gen2 as well?

> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
>  				 enum intel_pipe_crc_source source,
>  				 uint32_t *val)
> @@ -2039,7 +2053,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  	u32 val;
>  	int ret;
>  
> -	if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
> +	if (IS_VALLEYVIEW(dev))
>  		return -ENODEV;
>  
>  	if (pipe_crc->source == source)
> @@ -2049,7 +2063,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  	if (pipe_crc->source && source)
>  		return -EINVAL;
>  
> -	if (INTEL_INFO(dev)->gen < 5)
> +	if (IS_GEN2(dev))
> +		ret = i8xx_pipe_crc_ctl_reg(source, &val);
> +	else if (INTEL_INFO(dev)->gen < 5)
>  		ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
>  	else if (IS_GEN5(dev) || IS_GEN6(dev))
>  		ret = ilk_pipe_crc_ctl_reg(source, &val);
> -- 
> 1.8.4.rc3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC