[PATCH v2 00/18] 48-bit PPGTT

From: Michel Thierry <michel.thierry@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 00/18] 48-bit PPGTT
Date: Wed, 10 Jun 2015 17:46:37 +0100	[thread overview]
Message-ID: <1433954816-13787-1-git-send-email-michel.thierry@intel.com> (raw)

These are the rebased patches, after Mika's ppgtt clean-up series (and reusing
the macros added). New functions also follow these changes.

In order expand the GPU address space, a 4th level translation is added, the
Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255],
each pointing to a PDP. All the existing "dynamic alloc ppgtt" functions are
used, only adding the 4th level changes. I also updated some remaining
variables that were 32b only.

There are 2 hardware workarounds needed to allow correct operation with 48b
addresses (Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset). I added a
flag (I915_EXEC_SUPPORT_48BADDRESS) that will indicate if a given object can be
allocated outside the first 4 PDPs; if that's the case, insert will use the
DRM_MM_CREATE_TOP flag. I'm also including an igt test for this change.

This feature is only available in BDW and Gen9, requires LRC submission
mode (execlists) and setting i915.enable_ppgtt=3.

Also note that this expanded address space is only available for full PPGTT,
aliasing PPGTT remains 32b.

Michel Thierry (18):
  drm/i915/lrc: Update PDPx registers with lri commands
  drm/i915/gtt: Switch gen8_free_page_tables params
  drm/i915: Remove unnecessary gen8_clamp_pd
  drm/i915/gen8: Make pdp allocation more dynamic
  drm/i915/gen8: Abstract PDP usage
  drm/i915/gen8: Add dynamic page trace events
  drm/i915/gen8: implement alloc/free for 4lvl
  drm/i915/gen8: Add 4 level switching infrastructure and lrc support
  drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
  drm/i915/gen8: Pass sg_iter through pte inserts
  drm/i915/gen8: Add 4 level support in insert_entries and clear_range
  drm/i915/gen8: Initialize PDPs
  drm/i915: Expand error state's address width to 64b
  drm/i915/gen8: Add ppgtt info and debug_dump
  drm/i915: object size needs to be u64
  drm/i915: Check against correct user_size limit in 48b ppgtt mode
  drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
  drm/i915/gen8: Flip the 48b switch

 drivers/gpu/drm/i915/i915_debugfs.c        |  18 +-
 drivers/gpu/drm/i915/i915_drv.h            |  12 +-
 drivers/gpu/drm/i915/i915_gem.c            |  24 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  36 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 674 ++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_gem_gtt.h        |  66 ++-
 drivers/gpu/drm/i915/i915_gem_userptr.c    |  12 +-
 drivers/gpu/drm/i915/i915_gpu_error.c      |  17 +-
 drivers/gpu/drm/i915/i915_params.c         |   2 +-
 drivers/gpu/drm/i915/i915_reg.h            |   5 +-
 drivers/gpu/drm/i915/i915_trace.h          |  16 +
 drivers/gpu/drm/i915/intel_lrc.c           |  93 +++-
 include/uapi/drm/i915_drm.h                |   4 +-
 13 files changed, 809 insertions(+), 170 deletions(-)

-- 
2.4.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx