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From: Michel Thierry <michel.thierry@intel.com>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 01/18] drm/i915/lrc: Update PDPx registers with lri commands
Date: Mon, 22 Jun 2015 10:18:43 +0100	[thread overview]
Message-ID: <5587D2F3.3000309@intel.com> (raw)
In-Reply-To: <87r3pidsv4.fsf@gaia.fi.intel.com>

On 6/11/2015 7:04 PM, Mika Kuoppala wrote:
> Michel Thierry <michel.thierry@intel.com> writes:
>
>> A safer way to update the PDPx registers is sending lri commands, added
>> in the ring before the batchbuffer start. Otherwise, the ctx must be idle
>> before trying to change anything (but the ring-tail) in the ctx image. An
>> example where the ctx won't be idle is lite-restore.
>>
>> This patch depends on [1], and has the advantage that it doesn't require
>> to pre-allocate the top pdps like here [2].
>>
>> [1] http://mid.gmane.org/1432314314-23530-2-git-send-email-mika.kuoppala@intel.com
>> [2] http://mid.gmane.org/1432314314-23530-3-git-send-email-mika.kuoppala@intel.com
>>
>> v2: Combine lri writes (and save 8 commands). (Mika)
>>
>> Cc: Dave Gordon <david.s.gordon@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_lrc.c | 43 ++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 626949a..51c0e06 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1116,13 +1116,56 @@ static int gen9_init_render_ring(struct intel_engine_cs *ring)
>>   	return init_workarounds_ring(ring);
>>   }
>>
>> +static int intel_logical_ring_emit_pdps(struct intel_engine_cs *ring,
>> +					struct intel_context *ctx)
>> +{
>> +	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
>> +	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
>> +	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
>> +	int i, ret;
>> +
>> +	ret = intel_logical_ring_begin(ringbuf, ctx, num_lri_cmds * 2 + 2);
>> +	if (ret)
>> +		return ret;
>> +
>> +	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
>> +	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
>> +		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>> +
>> +		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
>> +		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
>> +		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
>> +		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
>> +	}
>> +
>> +	intel_logical_ring_emit(ringbuf, MI_NOOP);
>> +	intel_logical_ring_advance(ringbuf);
>> +
>> +	return 0;
>> +}
>> +
>>   static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
>>   			      struct intel_context *ctx,
>>   			      u64 offset, unsigned dispatch_flags)
>>   {
>> +	struct intel_engine_cs *ring = ringbuf->ring;
>>   	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
>>   	int ret;
>>
>> +	/* Don't rely in hw updating PDPs, specially in lite-restore.
>> +	 * Ideally, we should set Force PD Restore in ctx descriptor,
>> +	 * but we can't. Force Restore would be a second option, but
>> +	 * it is unsafe in case of lite-restore (because the ctx is
>> +	 * not idle). */
>> +	if (ctx->ppgtt &&
>
> Is this superfluous? Can the ctx->ppgtt ever be null with
> execlists?

It's for execlists with aliasing ppgtt. In that case ctx->ppgtt is null 
(and we shouldn't need to update the pdps).

-Michel

> -Mika
>
>
>> +	    (intel_ring_flag(ring) & ctx->ppgtt->pd_dirty_rings)) {
>> +		ret = intel_logical_ring_emit_pdps(ring, ctx);
>> +		if (ret)
>> +			return ret;
>> +
>> +		ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
>> +	}
>> +
>>   	ret = intel_logical_ring_begin(ringbuf, ctx, 4);
>>   	if (ret)
>>   		return ret;
>> --
>> 2.4.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2015-06-22  9:18 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-10 16:46 [PATCH v2 00/18] 48-bit PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 01/18] drm/i915/lrc: Update PDPx registers with lri commands Michel Thierry
2015-06-11 18:04   ` Mika Kuoppala
2015-06-22  9:18     ` Michel Thierry [this message]
2015-06-26 12:46   ` [PATCH v3] " Michel Thierry
2015-06-26 14:45     ` Mika Kuoppala
2015-06-10 16:46 ` [PATCH v2 02/18] drm/i915/gtt: Switch gen8_free_page_tables params Michel Thierry
2015-06-11 18:05   ` Mika Kuoppala
2015-06-26 16:38     ` Daniel Vetter
2015-06-10 16:46 ` [PATCH v2 03/18] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-06-10 16:46 ` [PATCH v2 04/18] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-06-10 16:46 ` [PATCH v2 05/18] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-06-10 16:46 ` [PATCH v2 06/18] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-06-10 16:46 ` [PATCH v2 07/18] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-06-10 16:46 ` [PATCH v2 08/18] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-06-10 16:46 ` [PATCH v2 09/18] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 10/18] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-06-10 16:46 ` [PATCH v2 11/18] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-06-10 16:46 ` [PATCH v2 12/18] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-06-10 16:46 ` [PATCH v2 13/18] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-06-10 16:46 ` [PATCH v2 14/18] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-06-10 16:46 ` [PATCH v2 15/18] drm/i915: object size needs to be u64 Michel Thierry
2015-06-10 16:46 ` [PATCH v2 16/18] drm/i915: Check against correct user_size limit in 48b ppgtt mode Michel Thierry
2015-06-10 17:57   ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 17/18] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-06-10 18:09   ` Chris Wilson
2015-06-17 12:49     ` Daniel Vetter
2015-06-17 12:53       ` Chris Wilson
2015-06-17 15:03         ` Daniel Vetter
2015-06-17 17:37           ` Chris Wilson
2015-06-18  6:45             ` Daniel Vetter
2015-06-18  7:03               ` Chris Wilson
2015-06-18  7:11                 ` Daniel Vetter
2015-06-18  7:34                   ` Chris Wilson
2015-06-23 12:21   ` [PATCH v3] " Michel Thierry
2015-06-23 13:22     ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 18/18] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-06-10 16:46 ` [PATCH v2] tests/gem_ppgtt: Check Wa32bitOffsets workarounds Michel Thierry
2015-07-01 15:27 ` [PATCH v3 00/17] 48-bit PPGTT Michel Thierry
2015-07-01 15:27   ` [PATCH v3 01/17] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-01 15:27   ` [PATCH v3 02/17] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-07 12:36     ` Goel, Akash
2015-07-07 12:56       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 03/17] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-07 12:43     ` Goel, Akash
2015-07-07 13:35       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 04/17] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-01 15:27   ` [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-07 12:48     ` Goel, Akash
2015-07-07 13:40       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 06/17] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-01 15:27   ` [PATCH v3 07/17] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-01 15:27   ` [PATCH v3 08/17] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-01 15:27   ` [PATCH v3 09/17] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-07 12:51     ` Goel, Akash
2015-07-07 13:42       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 10/17] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-07-01 15:27   ` [PATCH v3 11/17] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-07 12:53     ` Goel, Akash
2015-07-07 13:50       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 12/17] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-07 12:56     ` Goel, Akash
2015-07-07 13:51       ` Michel Thierry
2015-07-01 15:27   ` [PATCH v3 13/17] drm/i915: object size needs to be u64 Michel Thierry
2015-07-01 15:27   ` [PATCH v3 14/17] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-01 16:07     ` John Harrison
2015-07-01 15:27   ` [PATCH v3 15/17] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-01 15:31     ` Chris Wilson
2015-07-01 15:27   ` [PATCH v3 16/17] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-01 15:43     ` Chris Wilson
2015-07-01 15:54       ` Michel Thierry
2015-07-01 16:02     ` [PATCH v5] " Michel Thierry
2015-07-01 15:27   ` [PATCH v3 17/17] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-01 15:38   ` [PATCH v3 00/17] 48-bit PPGTT Daniel Vetter

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