Re: [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl

From: Michel Thierry <michel.thierry@intel.com>
To: "Goel, Akash" <akash.goel@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl
Date: Tue, 7 Jul 2015 14:40:10 +0100	[thread overview]
Message-ID: <559BD6BA.5070307@intel.com> (raw)
In-Reply-To: <559BCA8C.3010604@intel.com>

On 7/7/2015 1:48 PM, Goel, Akash wrote:
>
>
> On 7/1/2015 8:57 PM, Michel Thierry wrote:
>> @@ -1087,8 +1137,62 @@ static int gen8_alloc_va_range_4lvl(struct
>> i915_address_space *vm,
>>                       uint64_t start,
>>                       uint64_t length)
>>   {
>> -    WARN_ON(1); /* to be implemented later */
>> +    DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
>> +    struct i915_hw_ppgtt *ppgtt =
>> +        container_of(vm, struct i915_hw_ppgtt, base);
>> +    struct i915_page_directory_pointer *pdp;
>> +    const uint64_t orig_start = start;
>> +    const uint64_t orig_length = length;
>> +    uint64_t temp, pml4e;
>> +    int ret = 0;
>> +
>> +    /* Do the pml4 allocations first, so we don't need to track the
>> newly
>> +     * allocated tables below the pdp */
>> +    bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
>> +
>> +    /* The pagedirectory and pagetable allocations are done in the
>> shared 3
>> +     * and 4 level code. Just allocate the pdps.
>> +     */
>> +    gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
>> +        if (!pdp) {
>> +            WARN_ON(test_bit(pml4e, pml4->used_pml4es));
>> +            pdp = alloc_pdp(vm->dev);
>> +            if (IS_ERR(pdp))
>> +                goto err_out;
>> +
>> +            pml4->pdps[pml4e] = pdp;
>> +            __set_bit(pml4e, new_pdps);
>> +
>> trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, pml4e,
>> +                           pml4e << GEN8_PML4E_SHIFT,
> The ‘start’ variable should be used here in place of  ‘pml4e <<
> GEN8_PML4E_SHIFT’  ?

Correct, should be ‘start’.
Thanks

>> +                           GEN8_PML4E_SHIFT);
>> +        }
>> +    }
>> +

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