From: Bhupesh Sharma <bhupesh.sharma@freescale.com> To: <arnd@arndb.de>, <mark.rutland@arm.com>, <linux-arm-kernel@lists.infradead.org>, <marc.zyngier@arm.com>, <linux-clk@vger.kernel.org> Cc: <bhupesh.linux@gmail.com>, <Catalin.Marinas@arm.com>, <will.deacon@arm.com>, <bhupesh.sharma@freescale.com>, <olof@lixom.net> Subject: [PATCH v2 05/10] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs Date: Fri, 4 Sep 2015 12:27:47 +0530 [thread overview] Message-ID: <1441349872-4560-6-git-send-email-bhupesh.sharma@freescale.com> (raw) In-Reply-To: <1441349872-4560-1-git-send-email-bhupesh.sharma@freescale.com> This patch updates the 'clk-qoriq' device-tree bindings for chassis-3.0 compliant SoCs from FSL, for e.g. LS2080A Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- .../devicetree/bindings/clock/qoriq-clock.txt | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 16a3ec4..f0a4b1c 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -14,6 +14,7 @@ Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860 +3.0 ls2080a 1. Clock Block Binding @@ -32,9 +33,11 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" - Chassis-version clock strings include: + * "fsl,ls2080a-clockgen" + Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks + * "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks - reg: Describes the address of the device's resources within the address space defined by its parent bus, and resource zero represents the clock register set @@ -96,18 +99,23 @@ Required properties: - compatible : Should include one of the following: * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) + * "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0) * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) + * "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0) * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + * "fsl,qoriq-sysclk-3.0": for input system clock (v3.0). + It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0) - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0" + clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks. + For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency * 1 - equal to the PLL frequency divided by 2 -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: bhupesh.sharma@freescale.com (Bhupesh Sharma) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/10] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs Date: Fri, 4 Sep 2015 12:27:47 +0530 [thread overview] Message-ID: <1441349872-4560-6-git-send-email-bhupesh.sharma@freescale.com> (raw) In-Reply-To: <1441349872-4560-1-git-send-email-bhupesh.sharma@freescale.com> This patch updates the 'clk-qoriq' device-tree bindings for chassis-3.0 compliant SoCs from FSL, for e.g. LS2080A Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- .../devicetree/bindings/clock/qoriq-clock.txt | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 16a3ec4..f0a4b1c 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -14,6 +14,7 @@ Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860 +3.0 ls2080a 1. Clock Block Binding @@ -32,9 +33,11 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" - Chassis-version clock strings include: + * "fsl,ls2080a-clockgen" + Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks + * "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks - reg: Describes the address of the device's resources within the address space defined by its parent bus, and resource zero represents the clock register set @@ -96,18 +99,23 @@ Required properties: - compatible : Should include one of the following: * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) + * "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0) * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) + * "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0) * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + * "fsl,qoriq-sysclk-3.0": for input system clock (v3.0). + It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0) - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0" + clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks. + For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency * 1 - equal to the PLL frequency divided by 2 -- 1.7.9.5
next prev parent reply other threads:[~2015-09-04 6:59 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-09-04 6:57 [PATCH v2 00/10] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 6:57 ` [PATCH v2 01/10] arm64: Use generic Layerscape SoC family naming & rename LS2085A to LS2080A Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 16:31 ` Li Yang 2015-09-04 16:31 ` Li Yang 2015-09-04 20:10 ` Sharma Bhupesh 2015-09-04 20:10 ` Sharma Bhupesh 2015-09-08 20:24 ` Stuart Yoder 2015-09-08 20:24 ` Stuart Yoder 2015-09-09 3:54 ` Sharma Bhupesh 2015-09-09 3:54 ` Sharma Bhupesh 2015-09-04 6:57 ` [PATCH v2 02/10] Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 6:57 ` [PATCH v2 03/10] Documentation/dts: Add bindings for QIXIS FPGA controller found on FSL boards Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 16:56 ` Li Yang 2015-09-04 16:56 ` Li Yang 2015-09-04 20:16 ` Sharma Bhupesh 2015-09-04 20:16 ` Sharma Bhupesh 2015-09-04 20:16 ` Sharma Bhupesh 2015-09-04 21:12 ` Li Yang 2015-09-04 21:12 ` Li Yang 2015-09-04 21:12 ` Li Yang 2015-09-05 8:11 ` Sharma Bhupesh 2015-09-05 8:11 ` Sharma Bhupesh 2015-09-05 8:11 ` Sharma Bhupesh [not found] ` <BY1PR0301MB130339BD3B988DC938AA524482560-M1kb196zaoqj58cWwZvmNZwN6zqB+hSMnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org> 2015-09-09 23:38 ` Li Yang 2015-09-09 23:38 ` Li Yang 2015-09-09 23:38 ` Li Yang 2015-09-04 6:57 ` [PATCH v2 04/10] doc/bindings: Update PCIe devicetree binding documentation for LS2080A Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 17:56 ` Leo Li 2015-09-04 17:56 ` Leo Li 2015-09-04 20:20 ` Sharma Bhupesh 2015-09-04 20:20 ` Sharma Bhupesh 2015-09-04 20:20 ` Sharma Bhupesh 2015-09-06 2:25 ` Lian M.H. 2015-09-06 2:25 ` Lian M.H. 2015-09-06 2:25 ` Lian M.H. 2015-09-06 20:00 ` Sharma Bhupesh 2015-09-06 20:00 ` Sharma Bhupesh 2015-09-06 20:00 ` Sharma Bhupesh 2015-09-07 11:32 ` Arnd Bergmann 2015-09-07 11:32 ` Arnd Bergmann 2015-09-08 20:06 ` Li Yang 2015-09-08 20:06 ` Li Yang 2015-09-08 20:06 ` Li Yang 2015-09-09 3:45 ` Sharma Bhupesh 2015-09-09 3:45 ` Sharma Bhupesh 2015-09-09 3:45 ` Sharma Bhupesh 2015-09-09 9:07 ` Arnd Bergmann 2015-09-09 9:07 ` Arnd Bergmann 2015-09-09 9:07 ` Arnd Bergmann 2015-09-09 23:50 ` Li Yang 2015-09-09 23:50 ` Li Yang 2015-09-09 23:50 ` Li Yang 2015-09-10 1:52 ` Lian M.H. 2015-09-10 1:52 ` Lian M.H. 2015-09-10 1:52 ` Lian M.H. 2015-09-04 6:57 ` Bhupesh Sharma [this message] 2015-09-04 6:57 ` [PATCH v2 05/10] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs Bhupesh Sharma 2015-09-09 16:46 ` Scott Wood 2015-09-09 16:46 ` Scott Wood 2015-09-04 6:57 ` [PATCH v2 06/10] clk: qoriq: Add ls2080a support Bhupesh Sharma 2015-09-04 6:57 ` Bhupesh Sharma 2015-09-04 20:01 ` Li Yang 2015-09-04 20:01 ` Li Yang 2015-09-04 20:09 ` Sharma Bhupesh 2015-09-04 20:09 ` Sharma Bhupesh 2015-09-04 21:06 ` Li Yang 2015-09-04 21:06 ` Li Yang 2015-09-09 16:41 ` Scott Wood 2015-09-09 16:41 ` Scott Wood 2015-09-09 16:39 ` Scott Wood 2015-09-09 16:39 ` Scott Wood
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