Re: [PATCH v2 04/10] doc/bindings: Update PCIe devicetree binding documentation for LS2080A

From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Li Yang <leoli@freescale.com>,
	devicetree@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
	Bhupesh Sharma <bhupesh.sharma@freescale.com>,
	Catalin.Marinas@arm.com, olof@lixom.net, will.deacon@arm.com,
	Minghuan Lian <Minghuan.Lian@freescale.com>,
	marc.zyngier@arm.com, bhupesh.linux@gmail.com,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 04/10] doc/bindings: Update PCIe devicetree binding documentation for LS2080A
Date: Wed, 09 Sep 2015 11:07:14 +0200	[thread overview]
Message-ID: <5383634.Mln7J3sdWP@wuerfel> (raw)
In-Reply-To: <CADRPPNR-cSSQC5sLMmoqcxX46J6hdULa_V4v2BK7T8s8pcX0cg@mail.gmail.com>

On Tuesday 08 September 2015 15:06:16 Li Yang wrote:
> On Mon, Sep 7, 2015 at 6:32 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Friday 04 September 2015 12:27:46 Bhupesh Sharma wrote:
> >> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
> >>  and thus inherits all the common properties defined in designware-pcie.txt.
> >>
> >>  Required properties:
> >> -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
> >> +- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie",
> >> +  "fsl,ls2080a-pcie".
> >>  - reg: base addresses and lengths of the PCIe controller
> >>  - interrupts: A list of interrupt outputs of the controller. Must contain an
> >>    entry for each entry in the interrupt-names property.
> >>
> >
> > Are the two PCIe hosts mutually compatible? If they are, you should mandate
> > one of the strings as the base model for identification, with the additional
> > model being optional for identification of the specific SoC.
> 
> It seems that controllers on these chips are not exactly the same.
> They will get different driver data by matching the compatible
> strings.  Probably we could define a more generic compatible string,
> such as "fsl,layerscape-pcie" or "fsl,ls-pcie".
> 
> >
> > It would also be good to add a string with the specific version number of the
> > designware PCIe block that is being used there.
> 
> The binding has mentioned to reference the designware-pcie.txt.  But
> it might be more clear to mention the designware compatible string
> "snps,dw-pcie" again in the compatible part.  Currently there is no
> version number defined in the designware-pcie binding.  It might be
> hard to get this information for some SoCs.

For most of them, the information is available and then it should be
added. Obviously if you can't find it out, it's hard to guess and
you have to leave it out for that particular chip.

A lot of devices also have some internal version register that you
can read out.

	Arnd