From: Archit Taneja <architt@codeaurora.org>
To: dri-devel@lists.freedesktop.org, robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>
Subject: [PATCH v2 05/10] drm/msm/dsi: Parse bus clocks from a list
Date: Wed, 18 Nov 2015 16:25:26 +0530 [thread overview]
Message-ID: <1447844131-4182-6-git-send-email-architt@codeaurora.org> (raw)
In-Reply-To: <1447844131-4182-1-git-send-email-architt@codeaurora.org>
DSI bus clocks seem to vary between different DSI host versions, and the
SOC to which they belong. Even the enable/disable sequence varies.
Provide a list of bus clock names in dsi_cfg. The driver will use this to
retrieve the clocks, and enable/disable them.
Add bus clock lists for DSI6G, and DSI for MSM8916(this is DSI6G too, but
there is no MMSS_CC specific clock since there is no MMSS clock controller
on 8916).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 +++++-
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 107 ++++++++++++-------------------------
4 files changed, 53 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 8140e8b..7336b55 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -36,6 +36,7 @@ enum msm_dsi_phy_type {
};
#define DSI_DEV_REGULATOR_MAX 8
+#define DSI_BUS_CLK_MAX 4
/* Regulators for DSI devices */
struct dsi_reg_entry {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 5872d5e..c40044f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -18,6 +18,10 @@ static const struct msm_dsi_config dsi_v2_cfg = {
.io_offset = 0,
};
+static const char * const dsi_6g_bus_clk_names[] = {
+ "mdp_core_clk", "iface_clk", "bus_clk", "core_mmss_clk",
+};
+
static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
.io_offset = DSI_6G_REG_SHIFT,
.reg_cfg = {
@@ -29,6 +33,12 @@ static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
{"vddio", 1800000, 1800000, 100000, 100},
},
},
+ .bus_clk_names = dsi_6g_bus_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
+};
+
+static const char * const dsi_8916_bus_clk_names[] = {
+ "mdp_core_clk", "iface_clk", "bus_clk",
};
static const struct msm_dsi_config msm8916_dsi_cfg = {
@@ -42,6 +52,8 @@ static const struct msm_dsi_config msm8916_dsi_cfg = {
{"vddio", 1800000, 1800000, 100000, 100},
},
},
+ .bus_clk_names = dsi_8916_bus_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
};
static const struct msm_dsi_config msm8994_dsi_cfg = {
@@ -57,7 +69,9 @@ static const struct msm_dsi_config msm8994_dsi_cfg = {
{"lab_reg", -1, -1, -1, -1},
{"ibb_reg", -1, -1, -1, -1},
},
- }
+ },
+ .bus_clk_names = dsi_6g_bus_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
};
static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 4cf8872..5a36836 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -30,6 +30,8 @@
struct msm_dsi_config {
u32 io_offset;
struct dsi_reg_config reg_cfg;
+ const char * const *bus_clk_names;
+ const int num_bus_clks;
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index cbcf8dd..1da9adb2 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -103,10 +103,9 @@ struct msm_dsi_host {
void __iomem *ctrl_base;
struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
- struct clk *mdp_core_clk;
- struct clk *ahb_clk;
- struct clk *axi_clk;
- struct clk *mmss_misc_ahb_clk;
+
+ struct clk *bus_clks[DSI_BUS_CLK_MAX];
+
struct clk *byte_clk;
struct clk *esc_clk;
struct clk *pixel_clk;
@@ -319,40 +318,22 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host)
static int dsi_clk_init(struct msm_dsi_host *msm_host)
{
struct device *dev = &msm_host->pdev->dev;
- int ret = 0;
-
- msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk");
- if (IS_ERR(msm_host->mdp_core_clk)) {
- ret = PTR_ERR(msm_host->mdp_core_clk);
- pr_err("%s: Unable to get mdp core clk. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- msm_host->ahb_clk = devm_clk_get(dev, "iface_clk");
- if (IS_ERR(msm_host->ahb_clk)) {
- ret = PTR_ERR(msm_host->ahb_clk);
- pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
- if (IS_ERR(msm_host->axi_clk)) {
- ret = PTR_ERR(msm_host->axi_clk);
- pr_err("%s: Unable to get axi bus clk. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
- if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
- ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
- pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
- __func__, ret);
- goto exit;
+ const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
+ int i, ret = 0;
+
+ /* get bus clocks */
+ for (i = 0; i < cfg->num_bus_clks; i++) {
+ msm_host->bus_clks[i] = devm_clk_get(dev,
+ cfg->bus_clk_names[i]);
+ if (IS_ERR(msm_host->bus_clks[i])) {
+ ret = PTR_ERR(msm_host->bus_clks[i]);
+ pr_err("%s: Unable to get %s, ret = %d\n",
+ __func__, cfg->bus_clk_names[i], ret);
+ goto exit;
+ }
}
+ /* get link and source clocks */
msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
if (IS_ERR(msm_host->byte_clk)) {
ret = PTR_ERR(msm_host->byte_clk);
@@ -402,55 +383,37 @@ exit:
static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
{
- int ret;
+ const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
+ int i, ret;
DBG("id=%d", msm_host->id);
- ret = clk_prepare_enable(msm_host->mdp_core_clk);
- if (ret) {
- pr_err("%s: failed to enable mdp_core_clock, %d\n",
- __func__, ret);
- goto core_clk_err;
- }
-
- ret = clk_prepare_enable(msm_host->ahb_clk);
- if (ret) {
- pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
- goto ahb_clk_err;
- }
-
- ret = clk_prepare_enable(msm_host->axi_clk);
- if (ret) {
- pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
- goto axi_clk_err;
- }
-
- ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
- if (ret) {
- pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
- __func__, ret);
- goto misc_ahb_clk_err;
+ for (i = 0; i < cfg->num_bus_clks; i++) {
+ ret = clk_prepare_enable(msm_host->bus_clks[i]);
+ if (ret) {
+ pr_err("%s: failed to enable bus clock %d ret %d\n",
+ __func__, i, ret);
+ goto err;
+ }
}
return 0;
+err:
+ for (; i > 0; i--)
+ clk_disable_unprepare(msm_host->bus_clks[i]);
-misc_ahb_clk_err:
- clk_disable_unprepare(msm_host->axi_clk);
-axi_clk_err:
- clk_disable_unprepare(msm_host->ahb_clk);
-ahb_clk_err:
- clk_disable_unprepare(msm_host->mdp_core_clk);
-core_clk_err:
return ret;
}
static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
{
+ const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
+ int i;
+
DBG("");
- clk_disable_unprepare(msm_host->mmss_misc_ahb_clk);
- clk_disable_unprepare(msm_host->axi_clk);
- clk_disable_unprepare(msm_host->ahb_clk);
- clk_disable_unprepare(msm_host->mdp_core_clk);
+
+ for (i = cfg->num_bus_clks - 1; i >= 0; i--)
+ clk_disable_unprepare(msm_host->bus_clks[i]);
}
static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2015-11-18 10:56 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-14 12:58 [PATCH 00/12] drm/msm/dsi: Add support for DSI on MSM8960/APQ8064 Archit Taneja
2015-10-14 12:58 ` [PATCH 01/12] drm/msm/dsi: Update generated header for 8960 Archit Taneja
2015-10-14 12:58 ` [PATCH 02/12] drm/msm/dsi: Add support for 28nm PHY on 8960 Archit Taneja
2015-10-14 12:58 ` [PATCH 03/12] drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY Archit Taneja
2015-10-14 20:35 ` Stephen Boyd
2015-10-16 13:08 ` Archit Taneja
2015-10-16 18:28 ` Stephen Boyd
2015-10-14 12:58 ` [PATCH 04/12] drm/msm/dsi: Use a better way to figure out DSI version Archit Taneja
2015-10-14 12:58 ` [PATCH 05/12] drm/msm/dsi: Delay dsi_clk_init Archit Taneja
2015-10-14 12:58 ` [PATCH 06/12] drm/msm/dsi: Parse bus clocks from a list Archit Taneja
2015-10-14 12:58 ` [PATCH 07/12] drm/msm/dsi: Set up link clocks for DSIv2 Archit Taneja
2015-10-14 12:59 ` [PATCH 08/12] drm/msm/dsi: Add dsi_cfg for APQ8064 Archit Taneja
2015-10-14 12:59 ` [PATCH 09/12] drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2 Archit Taneja
2015-10-14 12:59 ` [PATCH 10/12] drm/msm/dsi: SFPB: Update generated headers Archit Taneja
2015-10-14 12:59 ` [PATCH 11/12] drm/msm/dsi: Enable MMSS SPFB port via syscon Archit Taneja
2015-10-14 12:59 ` [PATCH 12/12] dt-bindings: Add DSIv2 documentation Archit Taneja
2015-11-18 10:55 ` [PATCH v2 00/10] drm/msm/dsi: Add support for DSI on MSM8960/APQ8064 Archit Taneja
2015-11-18 10:55 ` [PATCH v2 01/10] drm/msm/dsi: Add support for 28nm PHY on 8960 Archit Taneja
2015-11-18 10:55 ` [PATCH v2 02/10] drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY Archit Taneja
2015-11-18 10:55 ` [PATCH v2 03/10] drm/msm/dsi: Use a better way to figure out DSI version Archit Taneja
2015-11-18 10:55 ` [PATCH v2 04/10] drm/msm/dsi: Delay dsi_clk_init Archit Taneja
2015-11-18 10:55 ` Archit Taneja [this message]
2015-11-18 10:55 ` [PATCH v2 06/10] drm/msm/dsi: Set up link clocks for DSIv2 Archit Taneja
2015-11-18 10:55 ` [PATCH v2 07/10] drm/msm/dsi: Add dsi_cfg for APQ8064 Archit Taneja
2015-11-18 10:55 ` [PATCH v2 08/10] drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2 Archit Taneja
2015-11-18 10:55 ` [PATCH v2 09/10] drm/msm/dsi: Enable MMSS SPFB port via syscon Archit Taneja
2015-11-18 10:55 ` [PATCH v2 10/10] dt-bindings: Add DSIv2 documentation Archit Taneja
2015-11-18 13:18 ` Rob Herring
2015-11-18 15:24 ` Archit Taneja
[not found] ` <564C981F.3040907-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-11-20 19:59 ` Rob Herring
2015-11-23 6:13 ` Archit Taneja
2015-12-02 8:20 ` Stephen Boyd
2015-12-02 8:34 ` Stephen Boyd
2015-12-07 6:51 ` Archit Taneja
2015-12-02 9:56 ` Archit Taneja
2015-12-03 7:16 ` Stephen Boyd
2015-12-03 11:11 ` Archit Taneja
2015-12-01 9:59 ` [PATCH v3 00/12] drm/msm/dsi: Add support for DSI on MSM8960/APQ8064 Archit Taneja
2015-12-01 9:59 ` [PATCH v3 01/12] drm/msm/dsi: Don't get byte/pixel source clocks from DT Archit Taneja
2015-12-01 10:00 ` [PATCH v3 02/12] drm/msm/dsi: Add support for 28nm PHY on 8960 Archit Taneja
2015-12-01 10:00 ` [PATCH v3 03/12] drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY Archit Taneja
2015-12-01 10:00 ` [PATCH v3 04/12] drm/msm/dsi: Use a better way to figure out DSI version Archit Taneja
2015-12-01 10:00 ` [PATCH v3 05/12] drm/msm/dsi: Delay dsi_clk_init Archit Taneja
2015-12-01 10:00 ` [PATCH v3 06/12] drm/msm/dsi: Parse bus clocks from a list Archit Taneja
2015-12-01 10:00 ` [PATCH v3 07/12] drm/msm/dsi: Set up link clocks for DSIv2 Archit Taneja
2015-12-01 10:00 ` [PATCH v3 08/12] drm/msm/dsi: Add dsi_cfg for APQ8064 Archit Taneja
2015-12-01 10:00 ` [PATCH v3 09/12] drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2 Archit Taneja
2015-12-01 10:00 ` [PATCH v3 10/12] drm/msm/dsi: Enable MMSS SPFB port via syscon Archit Taneja
2015-12-01 10:00 ` [PATCH v3 11/12] dt-bindings: msm/dsi: Fix the order in which clocks are listed Archit Taneja
2015-12-04 14:45 ` Rob Herring
2015-12-01 10:00 ` [PATCH v3 12/12] dt-bindings: msm/dsi: Add DSIv2 documentation Archit Taneja
2015-12-04 14:46 ` Rob Herring
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