From: Maxime Ripard <maxime.ripard@free-electrons.com> To: Mike Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, Chen-Yu Tsai <wens@csie.org> Cc: linux-clk@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>, Andre Przywara <andre.przywara@arm.com>, Rob Herring <robh+dt@kernel.org>, Vishnu Patekar <vishnupatekar0510@gmail.com>, linux-arm-kernel@lists.infradead.org, Boris Brezillon <boris.brezillon@free-electrons.com>, Maxime Ripard <maxime.ripard@free-electrons.com> Subject: [PATCH 08/16] clk: sunxi-ng: Add M-factor clock support Date: Sun, 8 May 2016 22:01:43 +0200 [thread overview] Message-ID: <1462737711-10017-9-git-send-email-maxime.ripard@free-electrons.com> (raw) In-Reply-To: <1462737711-10017-1-git-send-email-maxime.ripard@free-electrons.com> Introduce support for clocks that divide by a linear factor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_m.c | 135 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_m.h | 101 +++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu_m.c create mode 100644 drivers/clk/sunxi-ng/ccu_m.h diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a47a3bbdf285..f41de901c607 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -4,5 +4,6 @@ obj-y += ccu_reset.o obj-y += ccu_div_table.o obj-y += ccu_fixed_factor.o obj-y += ccu_gate.o +obj-y += ccu_m.o obj-y += ccu_mux.o obj-y += ccu_phase.o diff --git a/drivers/clk/sunxi-ng/ccu_m.c b/drivers/clk/sunxi-ng/ccu_m.c new file mode 100644 index 000000000000..424eb6da0d5b --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/clk-provider.h> + +#include "ccu_gate.h" +#include "ccu_m.h" +#include "ccu_mux.h" + +static void ccu_m_find_best(unsigned long parent, unsigned long rate, + unsigned int max_m, unsigned int *m) +{ + unsigned int _m = parent / rate; + + if (_m > max_m) + _m = max_m; + + *m = _m; +} + +static unsigned long ccu_m_round_rate(struct ccu_mux_internal *mux, + unsigned long parent_rate, + unsigned long rate, + void *data) +{ + struct ccu_m *cm = data; + unsigned int m; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + return parent_rate / m; +} + + +static void ccu_m_disable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_disable(&cm->common, cm->enable); +} + +static int ccu_m_enable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_enable(&cm->common, cm->enable); +} + +static int ccu_m_is_enabled(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_is_enabled(&cm->common, cm->enable); +} + +static unsigned long ccu_m_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long m; + u32 reg; + + reg = readl(cm->common.base + cm->common.reg); + + m = reg >> cm->m.shift; + m &= (1 << cm->m.width) - 1; + + return parent_rate / (m + 1); +} + +static int ccu_m_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_determine_rate(&cm->common, &cm->mux, + req, ccu_m_round_rate, cm); +} + +static int ccu_m_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long flags; + unsigned int m; + u32 reg; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + spin_lock_irqsave(cm->common.lock, flags); + + reg = readl(cm->common.base + cm->common.reg); + reg &= ((1 << cm->m.width) - 1) << cm->m.shift; + + writel(reg | ((m - 1) << cm->m.shift), + cm->common.base + cm->common.reg); + + spin_unlock_irqrestore(cm->common.lock, flags); + + return 0; +} + +static u8 ccu_m_get_parent(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_get_parent(&cm->common, &cm->mux); +} + +static int ccu_m_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); +} + +const struct clk_ops ccu_m_ops = { + .disable = ccu_m_disable, + .enable = ccu_m_enable, + .is_enabled = ccu_m_is_enabled, + + .get_parent = ccu_m_get_parent, + .set_parent = ccu_m_set_parent, + + .determine_rate = ccu_m_determine_rate, + .recalc_rate = ccu_m_recalc_rate, + .set_rate = ccu_m_set_rate, +}; diff --git a/drivers/clk/sunxi-ng/ccu_m.h b/drivers/clk/sunxi-ng/ccu_m.h new file mode 100644 index 000000000000..625c0a7cef43 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_M_H_ +#define _CCU_M_H_ + +#include <linux/clk-provider.h> + +#include "ccu_common.h" +#include "ccu_factor.h" +#include "ccu_mux.h" + +struct ccu_m { + u32 enable; + + struct ccu_factor m; + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, \ + _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_m *hw_to_ccu_m(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_m, common); +} + +extern const struct clk_ops ccu_m_ops; + +#endif /* _CCU_M_H_ */ -- 2.8.2
WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/16] clk: sunxi-ng: Add M-factor clock support Date: Sun, 8 May 2016 22:01:43 +0200 [thread overview] Message-ID: <1462737711-10017-9-git-send-email-maxime.ripard@free-electrons.com> (raw) In-Reply-To: <1462737711-10017-1-git-send-email-maxime.ripard@free-electrons.com> Introduce support for clocks that divide by a linear factor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_m.c | 135 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_m.h | 101 +++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu_m.c create mode 100644 drivers/clk/sunxi-ng/ccu_m.h diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a47a3bbdf285..f41de901c607 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -4,5 +4,6 @@ obj-y += ccu_reset.o obj-y += ccu_div_table.o obj-y += ccu_fixed_factor.o obj-y += ccu_gate.o +obj-y += ccu_m.o obj-y += ccu_mux.o obj-y += ccu_phase.o diff --git a/drivers/clk/sunxi-ng/ccu_m.c b/drivers/clk/sunxi-ng/ccu_m.c new file mode 100644 index 000000000000..424eb6da0d5b --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/clk-provider.h> + +#include "ccu_gate.h" +#include "ccu_m.h" +#include "ccu_mux.h" + +static void ccu_m_find_best(unsigned long parent, unsigned long rate, + unsigned int max_m, unsigned int *m) +{ + unsigned int _m = parent / rate; + + if (_m > max_m) + _m = max_m; + + *m = _m; +} + +static unsigned long ccu_m_round_rate(struct ccu_mux_internal *mux, + unsigned long parent_rate, + unsigned long rate, + void *data) +{ + struct ccu_m *cm = data; + unsigned int m; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + return parent_rate / m; +} + + +static void ccu_m_disable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_disable(&cm->common, cm->enable); +} + +static int ccu_m_enable(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_enable(&cm->common, cm->enable); +} + +static int ccu_m_is_enabled(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_gate_helper_is_enabled(&cm->common, cm->enable); +} + +static unsigned long ccu_m_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long m; + u32 reg; + + reg = readl(cm->common.base + cm->common.reg); + + m = reg >> cm->m.shift; + m &= (1 << cm->m.width) - 1; + + return parent_rate / (m + 1); +} + +static int ccu_m_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_determine_rate(&cm->common, &cm->mux, + req, ccu_m_round_rate, cm); +} + +static int ccu_m_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + unsigned long flags; + unsigned int m; + u32 reg; + + ccu_m_find_best(parent_rate, rate, 1 << cm->m.width, &m); + + spin_lock_irqsave(cm->common.lock, flags); + + reg = readl(cm->common.base + cm->common.reg); + reg &= ((1 << cm->m.width) - 1) << cm->m.shift; + + writel(reg | ((m - 1) << cm->m.shift), + cm->common.base + cm->common.reg); + + spin_unlock_irqrestore(cm->common.lock, flags); + + return 0; +} + +static u8 ccu_m_get_parent(struct clk_hw *hw) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_get_parent(&cm->common, &cm->mux); +} + +static int ccu_m_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_m *cm = hw_to_ccu_m(hw); + + return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); +} + +const struct clk_ops ccu_m_ops = { + .disable = ccu_m_disable, + .enable = ccu_m_enable, + .is_enabled = ccu_m_is_enabled, + + .get_parent = ccu_m_get_parent, + .set_parent = ccu_m_set_parent, + + .determine_rate = ccu_m_determine_rate, + .recalc_rate = ccu_m_recalc_rate, + .set_rate = ccu_m_set_rate, +}; diff --git a/drivers/clk/sunxi-ng/ccu_m.h b/drivers/clk/sunxi-ng/ccu_m.h new file mode 100644 index 000000000000..625c0a7cef43 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_m.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_M_H_ +#define _CCU_M_H_ + +#include <linux/clk-provider.h> + +#include "ccu_common.h" +#include "ccu_factor.h" +#include "ccu_mux.h" + +struct ccu_m { + u32 enable; + + struct ccu_factor m; + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, \ + _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT(_name, \ + _parent, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _flags) \ + struct ccu_m _struct = { \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_m _struct = { \ + .enable = _gate, \ + .m = SUNXI_CLK_FACTOR(_mshift, _mwidth), \ + .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_GATE, \ + .hw.init = SUNXI_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_m_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_m *hw_to_ccu_m(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_m, common); +} + +extern const struct clk_ops ccu_m_ops; + +#endif /* _CCU_M_H_ */ -- 2.8.2
next prev parent reply other threads:[~2016-05-08 20:01 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-08 20:01 [PATCH 00/16] clk: sunxi: introduce "modern" clock support Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 01/16] clk: fix critical clock locking Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-09 22:11 ` Stephen Boyd 2016-05-09 22:11 ` Stephen Boyd 2016-05-13 7:50 ` Maxime Ripard 2016-05-13 7:50 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 02/16] clk: sunxi-ng: Add common infrastructure Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-09 10:01 ` Chen-Yu Tsai 2016-05-09 10:01 ` Chen-Yu Tsai 2016-05-15 18:31 ` Maxime Ripard 2016-05-15 18:31 ` Maxime Ripard 2016-05-16 7:02 ` Chen-Yu Tsai 2016-05-16 7:02 ` Chen-Yu Tsai 2016-05-16 8:02 ` Jean-Francois Moine 2016-05-16 8:02 ` Jean-Francois Moine 2016-05-16 20:15 ` Maxime Ripard 2016-05-16 20:15 ` Maxime Ripard 2016-05-17 6:54 ` Jean-Francois Moine 2016-05-17 6:54 ` Jean-Francois Moine 2016-05-18 19:59 ` Maxime Ripard 2016-05-18 19:59 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 03/16] clk: sunxi-ng: Add fixed factor clock support Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-09 10:05 ` Chen-Yu Tsai 2016-05-09 10:05 ` Chen-Yu Tsai 2016-05-16 13:15 ` Jean-Francois Moine 2016-05-16 13:15 ` Jean-Francois Moine 2016-05-16 21:08 ` Maxime Ripard 2016-05-16 21:08 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 04/16] clk: sunxi-ng: Add gate " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 05/16] clk: sunxi-ng: Add mux " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-21 16:18 ` Chen-Yu Tsai 2016-05-21 16:18 ` Chen-Yu Tsai 2016-05-22 19:20 ` Maxime Ripard 2016-05-22 19:20 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 06/16] clk: sunxi-ng: Add divider table clock Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-21 16:30 ` Chen-Yu Tsai 2016-05-21 16:30 ` Chen-Yu Tsai 2016-05-08 20:01 ` [PATCH 07/16] clk: sunxi-ng: Add phase clock support Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-21 16:43 ` Chen-Yu Tsai 2016-05-21 16:43 ` Chen-Yu Tsai 2016-05-23 17:01 ` Maxime Ripard 2016-05-23 17:01 ` Maxime Ripard 2016-05-24 9:01 ` Chen-Yu Tsai 2016-05-24 9:01 ` Chen-Yu Tsai 2016-05-08 20:01 ` Maxime Ripard [this message] 2016-05-08 20:01 ` [PATCH 08/16] clk: sunxi-ng: Add M-factor " Maxime Ripard 2016-05-11 6:46 ` Jean-Francois Moine 2016-05-11 6:46 ` Jean-Francois Moine 2016-05-15 18:51 ` Maxime Ripard 2016-05-15 18:51 ` Maxime Ripard 2016-05-21 17:09 ` Chen-Yu Tsai 2016-05-21 17:09 ` Chen-Yu Tsai 2016-05-22 19:22 ` Maxime Ripard 2016-05-22 19:22 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 09/16] clk: sunxi-ng: Add P-factor " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 10/16] clk: sunxi-ng: Add M-P factor " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-23 13:45 ` Chen-Yu Tsai 2016-05-23 13:45 ` Chen-Yu Tsai 2016-05-23 17:18 ` Maxime Ripard 2016-05-23 17:18 ` Maxime Ripard 2016-05-24 4:14 ` Chen-Yu Tsai 2016-05-24 4:14 ` Chen-Yu Tsai 2016-05-24 21:07 ` Maxime Ripard 2016-05-24 21:07 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 11/16] clk: sunxi-ng: Add N-K-factor " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-23 13:58 ` Chen-Yu Tsai 2016-05-23 13:58 ` Chen-Yu Tsai 2016-05-08 20:01 ` [PATCH 12/16] clk: sunxi-ng: Add N-M-factor " Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-09 7:24 ` Jean-Francois Moine 2016-05-09 7:24 ` Jean-Francois Moine 2016-05-15 19:04 ` Maxime Ripard 2016-05-15 19:04 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 13/16] clk: sunxi-ng: Add N-K-M Factor clock Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-11 8:45 ` Jean-Francois Moine 2016-05-11 8:45 ` Jean-Francois Moine 2016-05-15 19:08 ` Maxime Ripard 2016-05-15 19:08 ` Maxime Ripard 2016-05-23 14:10 ` Chen-Yu Tsai 2016-05-23 14:10 ` Chen-Yu Tsai 2016-05-08 20:01 ` [PATCH 14/16] clk: sunxi-ng: Add N-K-M-P factor clock Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-11 8:49 ` Jean-Francois Moine 2016-05-11 8:49 ` Jean-Francois Moine 2016-05-23 14:36 ` Chen-Yu Tsai 2016-05-23 14:36 ` Chen-Yu Tsai 2016-05-30 7:57 ` Maxime Ripard 2016-05-30 7:57 ` Maxime Ripard 2016-05-08 20:01 ` [PATCH 15/16] clk: sunxi-ng: Add H3 clocks Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard 2016-05-09 7:39 ` Jean-Francois Moine 2016-05-09 7:39 ` Jean-Francois Moine 2016-05-15 19:18 ` Maxime Ripard 2016-05-15 19:18 ` Maxime Ripard 2016-05-13 9:45 ` Jean-Francois Moine 2016-05-13 9:45 ` Jean-Francois Moine 2016-05-18 14:02 ` Maxime Ripard 2016-05-18 14:02 ` Maxime Ripard 2016-05-18 16:23 ` Jean-Francois Moine 2016-05-18 16:23 ` Jean-Francois Moine 2016-05-18 16:27 ` Jean-Francois Moine 2016-05-18 16:27 ` Jean-Francois Moine 2016-05-16 13:47 ` Jean-Francois Moine 2016-05-16 13:47 ` Jean-Francois Moine 2016-05-18 21:20 ` Maxime Ripard 2016-05-18 21:20 ` Maxime Ripard 2016-05-30 16:15 ` Chen-Yu Tsai 2016-05-30 16:15 ` Chen-Yu Tsai 2016-06-01 19:19 ` Maxime Ripard 2016-06-01 19:19 ` Maxime Ripard 2016-06-03 6:42 ` Chen-Yu Tsai 2016-06-03 6:42 ` Chen-Yu Tsai 2016-06-03 6:55 ` Chen-Yu Tsai 2016-06-03 6:55 ` Chen-Yu Tsai 2016-05-08 20:01 ` [PATCH 16/16] ARM: dt: sun8i: switch the H3 to the new CCU driver Maxime Ripard 2016-05-08 20:01 ` Maxime Ripard
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