From: Zhi Mao <zhi.mao@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: <john@phrozen.org>, Thierry Reding <thierry.reding@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>, <linux-pwm@vger.kernel.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <yingjoe.chen@mediatek.com>,
<yt.shen@mediatek.com>, <sean.wang@mediatek.com>,
<zhenbao.liu@mediatek.com>
Subject: Re: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
Date: Thu, 6 Jul 2017 14:16:41 +0800 [thread overview]
Message-ID: <1499321801.22478.12.camel@mhfsdcap03> (raw)
In-Reply-To: <d009712e-f0a2-2dc7-2f64-ad8cfa21f98d@gmail.com>
On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>
> On 06/30/2017 08:05 AM, Zhi Mao wrote:
> > In original code, the pwm output frequency is not correct
> > when set bit<3>=1 to PWMCON register.
> >
> > Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
> > ---
> > drivers/pwm/pwm-mediatek.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> > index 5c11bc7..d08b5b3 100644
> > --- a/drivers/pwm/pwm-mediatek.c
> > +++ b/drivers/pwm/pwm-mediatek.c
> > @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > if (clkdiv > 7)
> > return -EINVAL;
> >
> > - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
> > + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
>
> Just for clarification, BIT(15) enables old PWM mode, which ignores
> CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and
> can be discarded.
>
> Am I correct? I took mt7623n datasheet for reference.
>
> Regards,
> Matthias
>
Yes, remove setting bit<3> will not take any effect.
PWMCON bit<3> is pwm source clock selecting register.
You can check the datasheet of MT7623 for details.
Regards
Zhi
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
> >
> >
WARNING: multiple messages have this Message-ID (diff)
From: Zhi Mao <zhi.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
To: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
zhenbao.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org
Subject: Re: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
Date: Thu, 6 Jul 2017 14:16:41 +0800 [thread overview]
Message-ID: <1499321801.22478.12.camel@mhfsdcap03> (raw)
In-Reply-To: <d009712e-f0a2-2dc7-2f64-ad8cfa21f98d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>
> On 06/30/2017 08:05 AM, Zhi Mao wrote:
> > In original code, the pwm output frequency is not correct
> > when set bit<3>=1 to PWMCON register.
> >
> > Signed-off-by: Zhi Mao <zhi.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > drivers/pwm/pwm-mediatek.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> > index 5c11bc7..d08b5b3 100644
> > --- a/drivers/pwm/pwm-mediatek.c
> > +++ b/drivers/pwm/pwm-mediatek.c
> > @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > if (clkdiv > 7)
> > return -EINVAL;
> >
> > - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
> > + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
>
> Just for clarification, BIT(15) enables old PWM mode, which ignores
> CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and
> can be discarded.
>
> Am I correct? I took mt7623n datasheet for reference.
>
> Regards,
> Matthias
>
Yes, remove setting bit<3> will not take any effect.
PWMCON bit<3> is pwm source clock selecting register.
You can check the datasheet of MT7623 for details.
Regards
Zhi
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
> >
> >
--
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WARNING: multiple messages have this Message-ID (diff)
From: zhi.mao@mediatek.com (Zhi Mao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
Date: Thu, 6 Jul 2017 14:16:41 +0800 [thread overview]
Message-ID: <1499321801.22478.12.camel@mhfsdcap03> (raw)
In-Reply-To: <d009712e-f0a2-2dc7-2f64-ad8cfa21f98d@gmail.com>
On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>
> On 06/30/2017 08:05 AM, Zhi Mao wrote:
> > In original code, the pwm output frequency is not correct
> > when set bit<3>=1 to PWMCON register.
> >
> > Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
> > ---
> > drivers/pwm/pwm-mediatek.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> > index 5c11bc7..d08b5b3 100644
> > --- a/drivers/pwm/pwm-mediatek.c
> > +++ b/drivers/pwm/pwm-mediatek.c
> > @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > if (clkdiv > 7)
> > return -EINVAL;
> >
> > - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
> > + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
>
> Just for clarification, BIT(15) enables old PWM mode, which ignores
> CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and
> can be discarded.
>
> Am I correct? I took mt7623n datasheet for reference.
>
> Regards,
> Matthias
>
Yes, remove setting bit<3> will not take any effect.
PWMCON bit<3> is pwm source clock selecting register.
You can check the datasheet of MT7623 for details.
Regards
Zhi
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
> >
> >
next prev parent reply other threads:[~2017-07-06 6:16 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-30 6:05 [PATCH v3 0/6] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` [PATCH v3 1/6] pwm: kconfig: modify mediatek information Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-08-21 7:31 ` Thierry Reding
2017-08-21 7:31 ` Thierry Reding
2017-06-30 6:05 ` [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-07-05 11:09 ` Matthias Brugger
2017-07-05 11:09 ` Matthias Brugger
2017-07-06 6:16 ` Zhi Mao [this message]
2017-07-06 6:16 ` Zhi Mao
2017-07-06 6:16 ` Zhi Mao
2017-07-06 6:43 ` Zhi Mao
2017-07-06 6:43 ` Zhi Mao
2017-07-06 6:43 ` Zhi Mao
2017-07-18 16:34 ` Matthias Brugger
2017-07-18 16:34 ` Matthias Brugger
2017-08-21 7:35 ` Thierry Reding
2017-08-21 7:35 ` Thierry Reding
2017-08-21 7:35 ` Thierry Reding
2017-06-30 6:05 ` [PATCH v3 3/6] pwm: mediatek: fix clock control issue Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-08-21 7:47 ` Thierry Reding
2017-08-21 7:47 ` Thierry Reding
2017-08-21 7:47 ` Thierry Reding
2017-06-30 6:05 ` [PATCH v3 4/6] pwm: bindings: add MT2712/MT7622 information Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-08-21 7:51 ` Thierry Reding
2017-08-21 7:51 ` Thierry Reding
2017-06-30 6:05 ` [PATCH v3 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-08-21 7:58 ` Thierry Reding
2017-08-21 7:58 ` Thierry Reding
2017-06-30 6:05 ` [PATCH v3 6/6] pwm: mediatek: add MT2712/MT7622 support Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-06-30 6:05 ` Zhi Mao
2017-08-21 8:05 ` Thierry Reding
2017-08-21 8:05 ` Thierry Reding
2017-08-21 9:05 ` Zhi Mao
2017-08-21 9:05 ` Zhi Mao
2017-08-21 9:05 ` Zhi Mao
2017-07-17 3:16 ` [PATCH v3 0/6] mediatek: pwm driver " Zhi Mao
2017-07-17 3:16 ` Zhi Mao
2017-07-17 3:16 ` Zhi Mao
2017-08-02 7:19 ` Zhi Mao
2017-08-02 7:19 ` Zhi Mao
2017-08-02 7:19 ` Zhi Mao
2017-08-02 8:42 ` John Crispin
2017-08-02 8:42 ` John Crispin
2017-08-02 8:42 ` John Crispin
2017-08-03 9:41 ` Zhi Mao
2017-08-03 9:41 ` Zhi Mao
2017-08-03 9:41 ` Zhi Mao
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