From: Chris Wilson <chris@chris-wilson.co.uk> To: Tvrtko Ursulin <tursulin@ursulin.net>, igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org Subject: Re: [PATH i-g-t v12 2/2] tests: add slice power programming test Date: Wed, 12 Sep 2018 12:53:43 +0100 [thread overview] Message-ID: <153675322311.13043.17778315701113692275@skylake-alporthouse-com> (raw) In-Reply-To: <20180911144210.16613-1-tvrtko.ursulin@linux.intel.com> Quoting Tvrtko Ursulin (2018-09-11 15:42:10) > + last_with_engines = -1; > + for (class = 0; class < ~0; class++) { > + for (instance = 0; instance < ~0; instance++) { > + int ret; > + > + sseu.class = class; > + sseu.instance = instance; > + > + ret = __gem_context_set_param(fd, &arg); > + > + if (has_engine(fd, class, instance)) { > + if (engine_supports_sseu(fd, class, instance)) Meh, <rant>. I just don't like having hardcoded db on this side of the ABI. The ABI imo is to ask the kernel if the device/engine is supported, and should not allow for assumptions. > +static void > +test_dynamic(int fd, unsigned int flags) > +{ > + uint64_t pg_slice_mask = mask_minus_one(__slice_mask__); > + unsigned int pg_slice_count = __slice_count__ - 1; > + struct drm_i915_gem_context_param_sseu sseu = { }; > + struct drm_i915_gem_context_param arg = > + { .param = I915_CONTEXT_PARAM_SSEU, > + .ctx_id = gem_context_create(fd), > + .size = sizeof(sseu), > + .value = to_user_pointer(&sseu) }; > + igt_spin_t *spin = NULL; > + > + gem_context_get_param(fd, &arg); > + > + /* First set the default mask */ > + if (flags & TEST_BUSY) > + spin = __spin_sync(fd, arg.ctx_id, I915_EXEC_RENDER); > + > + sseu.slice_mask = __slice_mask__; > + gem_context_set_param(fd, &arg); I would also suggest a reset test here. Both reset when idle, and by hangcheck/forced-reset of the spinner & active context. And across suspend. > + igt_assert_eq(read_slice_count_busy(fd, arg.ctx_id, 0, spin), > + __slice_count__); > + igt_assert_eq(read_slice_count(fd, 0, 0), __slice_count__); In the read_slice I would suggest having a igt_assert(gem_bo_busy(spin->handle)); -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: Tvrtko Ursulin <tursulin@ursulin.net>, igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org Subject: Re: [igt-dev] [Intel-gfx] [PATH i-g-t v12 2/2] tests: add slice power programming test Date: Wed, 12 Sep 2018 12:53:43 +0100 [thread overview] Message-ID: <153675322311.13043.17778315701113692275@skylake-alporthouse-com> (raw) In-Reply-To: <20180911144210.16613-1-tvrtko.ursulin@linux.intel.com> Quoting Tvrtko Ursulin (2018-09-11 15:42:10) > + last_with_engines = -1; > + for (class = 0; class < ~0; class++) { > + for (instance = 0; instance < ~0; instance++) { > + int ret; > + > + sseu.class = class; > + sseu.instance = instance; > + > + ret = __gem_context_set_param(fd, &arg); > + > + if (has_engine(fd, class, instance)) { > + if (engine_supports_sseu(fd, class, instance)) Meh, <rant>. I just don't like having hardcoded db on this side of the ABI. The ABI imo is to ask the kernel if the device/engine is supported, and should not allow for assumptions. > +static void > +test_dynamic(int fd, unsigned int flags) > +{ > + uint64_t pg_slice_mask = mask_minus_one(__slice_mask__); > + unsigned int pg_slice_count = __slice_count__ - 1; > + struct drm_i915_gem_context_param_sseu sseu = { }; > + struct drm_i915_gem_context_param arg = > + { .param = I915_CONTEXT_PARAM_SSEU, > + .ctx_id = gem_context_create(fd), > + .size = sizeof(sseu), > + .value = to_user_pointer(&sseu) }; > + igt_spin_t *spin = NULL; > + > + gem_context_get_param(fd, &arg); > + > + /* First set the default mask */ > + if (flags & TEST_BUSY) > + spin = __spin_sync(fd, arg.ctx_id, I915_EXEC_RENDER); > + > + sseu.slice_mask = __slice_mask__; > + gem_context_set_param(fd, &arg); I would also suggest a reset test here. Both reset when idle, and by hangcheck/forced-reset of the spinner & active context. And across suspend. > + igt_assert_eq(read_slice_count_busy(fd, arg.ctx_id, 0, spin), > + __slice_count__); > + igt_assert_eq(read_slice_count(fd, 0, 0), __slice_count__); In the read_slice I would suggest having a igt_assert(gem_bo_busy(spin->handle)); -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev
next prev parent reply other threads:[~2018-09-12 11:53 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-09-05 14:25 [PATH i-g-t 0/2] Per context dynamic (sub)slice power-gating Tvrtko Ursulin 2018-09-05 14:25 ` [igt-dev] " Tvrtko Ursulin 2018-09-05 14:25 ` [PATH i-g-t 1/2] headers: bump Tvrtko Ursulin 2018-09-05 14:25 ` [igt-dev] " Tvrtko Ursulin 2018-09-05 14:25 ` [PATH i-g-t 2/2] tests: add slice power programming test Tvrtko Ursulin 2018-09-05 14:25 ` [igt-dev] " Tvrtko Ursulin 2018-09-05 22:57 ` Chris Wilson 2018-09-05 22:57 ` Chris Wilson 2018-09-06 7:00 ` Chris Wilson 2018-09-06 7:00 ` Chris Wilson 2018-09-06 9:31 ` Tvrtko Ursulin 2018-09-06 9:31 ` [igt-dev] [Intel-gfx] " Tvrtko Ursulin 2018-09-06 9:50 ` [igt-dev] " Chris Wilson 2018-09-06 9:50 ` [igt-dev] [Intel-gfx] " Chris Wilson 2018-09-11 11:34 ` [PATH i-g-t v11 " Tvrtko Ursulin 2018-09-11 11:34 ` [igt-dev] " Tvrtko Ursulin 2018-09-11 11:45 ` Chris Wilson 2018-09-11 11:45 ` Chris Wilson 2018-09-11 12:00 ` Tvrtko Ursulin 2018-09-11 12:00 ` [Intel-gfx] " Tvrtko Ursulin 2018-09-11 14:42 ` [PATH i-g-t v12 " Tvrtko Ursulin 2018-09-11 14:42 ` [igt-dev] " Tvrtko Ursulin 2018-09-12 11:53 ` Chris Wilson [this message] 2018-09-12 11:53 ` [igt-dev] [Intel-gfx] " Chris Wilson 2018-09-13 10:38 ` Tvrtko Ursulin 2018-09-13 10:38 ` [igt-dev] [Intel-gfx] " Tvrtko Ursulin 2018-09-13 10:48 ` Chris Wilson 2018-09-13 10:48 ` [igt-dev] [Intel-gfx] " Chris Wilson 2018-09-14 16:04 ` [PATCH i-g-t v13 2/2] tests/gem_ctx_sseu: Dynamic (sub)slice programming tests Tvrtko Ursulin 2018-09-14 16:04 ` [Intel-gfx] " Tvrtko Ursulin 2018-09-14 16:07 ` [igt-dev] " Chris Wilson 2018-09-14 16:07 ` Chris Wilson 2018-09-14 16:17 ` Chris Wilson 2018-09-14 16:17 ` Chris Wilson 2018-09-17 9:33 ` Tvrtko Ursulin 2018-09-17 9:33 ` [Intel-gfx] " Tvrtko Ursulin 2018-09-17 10:38 ` Chris Wilson 2018-09-17 10:38 ` [Intel-gfx] " Chris Wilson 2018-09-17 11:28 ` [PATCH i-g-t v14 " Tvrtko Ursulin 2018-09-17 11:28 ` [Intel-gfx] " Tvrtko Ursulin 2018-09-17 12:04 ` [igt-dev] " Chris Wilson 2018-09-17 12:04 ` Chris Wilson 2018-09-18 13:41 ` [PATCH i-g-t v15 " Tvrtko Ursulin 2018-09-18 13:41 ` [igt-dev] " Tvrtko Ursulin 2018-09-05 16:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating Patchwork 2018-09-05 22:44 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2018-09-11 18:13 ` [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev3) Patchwork 2018-09-11 23:31 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2018-09-14 17:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev4) Patchwork 2018-09-14 22:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2018-09-17 12:21 ` [igt-dev] ✗ Fi.CI.BAT: failure for Per context dynamic (sub)slice power-gating (rev5) Patchwork 2018-09-17 18:21 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2018-09-17 20:43 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2018-09-18 14:02 ` [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev6) Patchwork 2018-09-18 15:18 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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