From: Ludovic Barre <ludovic.Barre@st.com>
To: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
<benjamin.gaignard@linaro.org>,
Gerald Baeza <gerald.baeza@st.com>,
Loic Pallardy <loic.pallardy@st.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-mmc@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
Ludovic Barre <ludovic.barre@st.com>
Subject: [PATCH V2 25/27] mmc: mmci: add stm32 sdmmc registers
Date: Fri, 21 Sep 2018 11:46:19 +0200 [thread overview]
Message-ID: <1537523181-14578-26-git-send-email-ludovic.Barre@st.com> (raw)
In-Reply-To: <1537523181-14578-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/mmc/host/mmci.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index b4a8de5..75b9c5c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -23,6 +23,14 @@
#define MCI_ST_DATA31DIREN (1 << 5)
#define MCI_ST_FBCLKEN (1 << 7)
#define MCI_ST_DATA74DIREN (1 << 8)
+/*
+ * The STM32 sdmmc does not have PWR_UP/OD/ROD
+ * and uses the power register for
+ */
+#define MCI_STM32_PWR_CYC 0x02
+#define MCI_STM32_VSWITCH BIT(2)
+#define MCI_STM32_VSWITCHEN BIT(3)
+#define MCI_STM32_DIRPOL BIT(4)
#define MMCICLOCK 0x004
#define MCI_CLK_ENABLE (1 << 8)
@@ -50,6 +58,19 @@
#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
+/* Modified on STM32 sdmmc */
+#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
+#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
+#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
+#define MCI_STM32_CLK_NEGEDGE BIT(16)
+#define MCI_STM32_CLK_HWFCEN BIT(17)
+#define MCI_STM32_CLK_DDR BIT(18)
+#define MCI_STM32_CLK_BUSSPEED BIT(19)
+#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
+#define MCI_STM32_CLK_SELCK (0 << 20)
+#define MCI_STM32_CLK_SELCKIN (1 << 20)
+#define MCI_STM32_CLK_SELFBCK (2 << 20)
+
#define MMCIARGUMENT 0x008
/* The command register controls the Command Path State Machine (CPSM) */
@@ -72,6 +93,15 @@
#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
+/* Command register in STM32 sdmmc versions */
+#define MCI_CPSM_STM32_CMDTRANS BIT(6)
+#define MCI_CPSM_STM32_CMDSTOP BIT(7)
+#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
+#define MCI_CPSM_STM32_NORSP (0 << 8)
+#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
+#define MCI_CPSM_STM32_SRSP (2 << 8)
+#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
+#define MCI_CPSM_STM32_ENABLE BIT(12)
#define MMCIRESPCMD 0x010
#define MMCIRESPONSE0 0x014
@@ -130,6 +160,8 @@
#define MCI_ST_SDIOIT (1 << 22)
#define MCI_ST_CEATAEND (1 << 23)
#define MCI_ST_CARDBUSY (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0 BIT(20)
#define MMCICLEAR 0x038
#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -175,11 +207,32 @@
#define MCI_ST_SDIOITMASK (1 << 22)
#define MCI_ST_CEATAENDMASK (1 << 23)
#define MCI_ST_BUSYENDMASK (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0ENDMASK BIT(21)
#define MMCIMASK1 0x040
#define MMCIFIFOCNT 0x048
#define MMCIFIFO 0x080 /* to 0x0bc */
+/* STM32 sdmmc registers for IDMA (Internal DMA) */
+#define MMCI_STM32_IDMACTRLR 0x050
+#define MMCI_STM32_IDMAEN BIT(0)
+#define MMCI_STM32_IDMALLIEN BIT(1)
+
+#define MMCI_STM32_IDMABSIZER 0x054
+#define MMCI_STM32_IDMABNDT_SHIFT 5
+#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
+
+#define MMCI_STM32_IDMABASE0R 0x058
+
+#define MMCI_STM32_IDMALAR 0x64
+#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
+#define MMCI_STM32_ABR BIT(29)
+#define MMCI_STM32_ULS BIT(30)
+#define MMCI_STM32_ULA BIT(31)
+
+#define MMCI_STM32_IDMABAR 0x68
+
#define MCI_IRQENABLE \
(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
@@ -190,6 +243,9 @@
(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
MCI_TXFIFOHALFEMPTYMASK)
+#define MCI_IRQ_PIO_STM32_MASK \
+ (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
+
#define NR_SG 128
#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Ludovic Barre <ludovic.Barre@st.com>
To: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
benjamin.gaignard@linaro.org, Gerald Baeza <gerald.baeza@st.com>,
Loic Pallardy <loic.pallardy@st.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-mmc@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
Ludovic Barre <ludovic.barre@st.com>
Subject: [PATCH V2 25/27] mmc: mmci: add stm32 sdmmc registers
Date: Fri, 21 Sep 2018 11:46:19 +0200 [thread overview]
Message-ID: <1537523181-14578-26-git-send-email-ludovic.Barre@st.com> (raw)
In-Reply-To: <1537523181-14578-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/mmc/host/mmci.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index b4a8de5..75b9c5c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -23,6 +23,14 @@
#define MCI_ST_DATA31DIREN (1 << 5)
#define MCI_ST_FBCLKEN (1 << 7)
#define MCI_ST_DATA74DIREN (1 << 8)
+/*
+ * The STM32 sdmmc does not have PWR_UP/OD/ROD
+ * and uses the power register for
+ */
+#define MCI_STM32_PWR_CYC 0x02
+#define MCI_STM32_VSWITCH BIT(2)
+#define MCI_STM32_VSWITCHEN BIT(3)
+#define MCI_STM32_DIRPOL BIT(4)
#define MMCICLOCK 0x004
#define MCI_CLK_ENABLE (1 << 8)
@@ -50,6 +58,19 @@
#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
+/* Modified on STM32 sdmmc */
+#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
+#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
+#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
+#define MCI_STM32_CLK_NEGEDGE BIT(16)
+#define MCI_STM32_CLK_HWFCEN BIT(17)
+#define MCI_STM32_CLK_DDR BIT(18)
+#define MCI_STM32_CLK_BUSSPEED BIT(19)
+#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
+#define MCI_STM32_CLK_SELCK (0 << 20)
+#define MCI_STM32_CLK_SELCKIN (1 << 20)
+#define MCI_STM32_CLK_SELFBCK (2 << 20)
+
#define MMCIARGUMENT 0x008
/* The command register controls the Command Path State Machine (CPSM) */
@@ -72,6 +93,15 @@
#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
+/* Command register in STM32 sdmmc versions */
+#define MCI_CPSM_STM32_CMDTRANS BIT(6)
+#define MCI_CPSM_STM32_CMDSTOP BIT(7)
+#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
+#define MCI_CPSM_STM32_NORSP (0 << 8)
+#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
+#define MCI_CPSM_STM32_SRSP (2 << 8)
+#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
+#define MCI_CPSM_STM32_ENABLE BIT(12)
#define MMCIRESPCMD 0x010
#define MMCIRESPONSE0 0x014
@@ -130,6 +160,8 @@
#define MCI_ST_SDIOIT (1 << 22)
#define MCI_ST_CEATAEND (1 << 23)
#define MCI_ST_CARDBUSY (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0 BIT(20)
#define MMCICLEAR 0x038
#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -175,11 +207,32 @@
#define MCI_ST_SDIOITMASK (1 << 22)
#define MCI_ST_CEATAENDMASK (1 << 23)
#define MCI_ST_BUSYENDMASK (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0ENDMASK BIT(21)
#define MMCIMASK1 0x040
#define MMCIFIFOCNT 0x048
#define MMCIFIFO 0x080 /* to 0x0bc */
+/* STM32 sdmmc registers for IDMA (Internal DMA) */
+#define MMCI_STM32_IDMACTRLR 0x050
+#define MMCI_STM32_IDMAEN BIT(0)
+#define MMCI_STM32_IDMALLIEN BIT(1)
+
+#define MMCI_STM32_IDMABSIZER 0x054
+#define MMCI_STM32_IDMABNDT_SHIFT 5
+#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
+
+#define MMCI_STM32_IDMABASE0R 0x058
+
+#define MMCI_STM32_IDMALAR 0x64
+#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
+#define MMCI_STM32_ABR BIT(29)
+#define MMCI_STM32_ULS BIT(30)
+#define MMCI_STM32_ULA BIT(31)
+
+#define MMCI_STM32_IDMABAR 0x68
+
#define MCI_IRQENABLE \
(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
@@ -190,6 +243,9 @@
(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
MCI_TXFIFOHALFEMPTYMASK)
+#define MCI_IRQ_PIO_STM32_MASK \
+ (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
+
#define NR_SG 128
#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: ludovic.Barre@st.com (Ludovic Barre)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 25/27] mmc: mmci: add stm32 sdmmc registers
Date: Fri, 21 Sep 2018 11:46:19 +0200 [thread overview]
Message-ID: <1537523181-14578-26-git-send-email-ludovic.Barre@st.com> (raw)
In-Reply-To: <1537523181-14578-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/mmc/host/mmci.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index b4a8de5..75b9c5c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -23,6 +23,14 @@
#define MCI_ST_DATA31DIREN (1 << 5)
#define MCI_ST_FBCLKEN (1 << 7)
#define MCI_ST_DATA74DIREN (1 << 8)
+/*
+ * The STM32 sdmmc does not have PWR_UP/OD/ROD
+ * and uses the power register for
+ */
+#define MCI_STM32_PWR_CYC 0x02
+#define MCI_STM32_VSWITCH BIT(2)
+#define MCI_STM32_VSWITCHEN BIT(3)
+#define MCI_STM32_DIRPOL BIT(4)
#define MMCICLOCK 0x004
#define MCI_CLK_ENABLE (1 << 8)
@@ -50,6 +58,19 @@
#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
+/* Modified on STM32 sdmmc */
+#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
+#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
+#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
+#define MCI_STM32_CLK_NEGEDGE BIT(16)
+#define MCI_STM32_CLK_HWFCEN BIT(17)
+#define MCI_STM32_CLK_DDR BIT(18)
+#define MCI_STM32_CLK_BUSSPEED BIT(19)
+#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
+#define MCI_STM32_CLK_SELCK (0 << 20)
+#define MCI_STM32_CLK_SELCKIN (1 << 20)
+#define MCI_STM32_CLK_SELFBCK (2 << 20)
+
#define MMCIARGUMENT 0x008
/* The command register controls the Command Path State Machine (CPSM) */
@@ -72,6 +93,15 @@
#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
+/* Command register in STM32 sdmmc versions */
+#define MCI_CPSM_STM32_CMDTRANS BIT(6)
+#define MCI_CPSM_STM32_CMDSTOP BIT(7)
+#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
+#define MCI_CPSM_STM32_NORSP (0 << 8)
+#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
+#define MCI_CPSM_STM32_SRSP (2 << 8)
+#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
+#define MCI_CPSM_STM32_ENABLE BIT(12)
#define MMCIRESPCMD 0x010
#define MMCIRESPONSE0 0x014
@@ -130,6 +160,8 @@
#define MCI_ST_SDIOIT (1 << 22)
#define MCI_ST_CEATAEND (1 << 23)
#define MCI_ST_CARDBUSY (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0 BIT(20)
#define MMCICLEAR 0x038
#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -175,11 +207,32 @@
#define MCI_ST_SDIOITMASK (1 << 22)
#define MCI_ST_CEATAENDMASK (1 << 23)
#define MCI_ST_BUSYENDMASK (1 << 24)
+/* Extended status bits for the STM32 variants */
+#define MCI_STM32_BUSYD0ENDMASK BIT(21)
#define MMCIMASK1 0x040
#define MMCIFIFOCNT 0x048
#define MMCIFIFO 0x080 /* to 0x0bc */
+/* STM32 sdmmc registers for IDMA (Internal DMA) */
+#define MMCI_STM32_IDMACTRLR 0x050
+#define MMCI_STM32_IDMAEN BIT(0)
+#define MMCI_STM32_IDMALLIEN BIT(1)
+
+#define MMCI_STM32_IDMABSIZER 0x054
+#define MMCI_STM32_IDMABNDT_SHIFT 5
+#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
+
+#define MMCI_STM32_IDMABASE0R 0x058
+
+#define MMCI_STM32_IDMALAR 0x64
+#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
+#define MMCI_STM32_ABR BIT(29)
+#define MMCI_STM32_ULS BIT(30)
+#define MMCI_STM32_ULA BIT(31)
+
+#define MMCI_STM32_IDMABAR 0x68
+
#define MCI_IRQENABLE \
(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
@@ -190,6 +243,9 @@
(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
MCI_TXFIFOHALFEMPTYMASK)
+#define MCI_IRQ_PIO_STM32_MASK \
+ (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
+
#define NR_SG 128
#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
--
2.7.4
next prev parent reply other threads:[~2018-09-21 9:47 UTC|newest]
Thread overview: 136+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-21 9:45 [PATCH V2 00/27] mmc: mmci: add sdmmc variant for stm32 Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` [PATCH V2 01/27] mmc: mmci: internalize dma map/unmap into mmci dma functions Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-26 23:49 ` Ulf Hansson
2018-09-26 23:49 ` Ulf Hansson
2018-09-21 9:45 ` [PATCH V2 02/27] mmc: mmci: internalize dma_inprogress " Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-26 23:49 ` Ulf Hansson
2018-09-26 23:49 ` Ulf Hansson
2018-09-21 9:45 ` [PATCH V2 03/27] mmc: mmci: convert dma_setup callback to return an int Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-24 14:28 ` Ulf Hansson
2018-09-24 14:28 ` Ulf Hansson
2018-09-24 16:12 ` Ludovic BARRE
2018-09-24 16:12 ` Ludovic BARRE
2018-09-24 16:12 ` Ludovic BARRE
2018-09-26 23:49 ` Ulf Hansson
2018-09-26 23:49 ` Ulf Hansson
2018-09-27 8:55 ` Srinivas Kandagatla
2018-09-27 8:55 ` Srinivas Kandagatla
2018-09-21 9:45 ` [PATCH V2 04/27] mmc: mmci: introduce dma_priv pointer to mmci_host Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-24 18:52 ` Ulf Hansson
2018-09-24 18:52 ` Ulf Hansson
2018-09-25 7:19 ` Ludovic BARRE
2018-09-25 7:19 ` Ludovic BARRE
2018-09-25 7:19 ` Ludovic BARRE
2018-09-21 9:45 ` [PATCH V2 05/27] mmc: mmci: move mmci next cookie to mci host Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-21 9:45 ` Ludovic Barre
2018-09-24 18:46 ` Ulf Hansson
2018-09-24 18:46 ` Ulf Hansson
2018-09-25 7:08 ` Ludovic BARRE
2018-09-25 7:08 ` Ludovic BARRE
2018-09-25 7:08 ` Ludovic BARRE
2018-09-21 9:46 ` [PATCH V2 06/27] mmc: mmci: merge prepare data functions Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 07/27] mmc: mmci: add prepare/unprepare_data callbacks Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 08/27] mmc: mmci: add get_next_data callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 09/27] mmc: mmci: modify dma_setup callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-10-01 9:30 ` Ulf Hansson
2018-10-01 9:30 ` Ulf Hansson
2018-10-01 9:43 ` Ludovic BARRE
2018-10-01 9:43 ` Ludovic BARRE
2018-10-01 9:43 ` Ludovic BARRE
2018-09-21 9:46 ` [PATCH V2 10/27] mmc: mmci: add dma_release callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 11/27] mmc: mmci: add dma_start callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 12/27] mmc: mmci: add dma_finalize callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 13/27] mmc: mmci: add dma_error callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 14/27] mmc: mmci: add validate_data callback Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 15/27] mmc: mmci: add set_clk/pwrreg callbacks Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 16/27] mmc: mmci: add datactrl block size variant property Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 17/27] mmc: mmci: expand startbiterr to irqmask and error check Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 18/27] mmc: mmci: add variant properties to define cpsm & cmdresp bits Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 19/27] mmc: mmci: add variant property to define dpsm bit Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 20/27] mmc: mmci: add variant property to define irq pio mask Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 21/27] mmc: mmci: add variant property to write datactrl before command Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 22/27] mmc: mmci: add variant property to not read datacnt Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 23/27] mmc: mmci: add variant property to request a reset Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-10-01 9:30 ` Ulf Hansson
2018-10-01 9:30 ` Ulf Hansson
2018-10-01 12:16 ` Ludovic BARRE
2018-10-01 12:16 ` Ludovic BARRE
2018-10-01 12:16 ` Ludovic BARRE
2018-10-01 13:43 ` Ulf Hansson
2018-10-01 13:43 ` Ulf Hansson
2018-09-21 9:46 ` [PATCH V2 24/27] mmc: mmci: add clock divider for stm32 sdmmc Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre [this message]
2018-09-21 9:46 ` [PATCH V2 25/27] mmc: mmci: add stm32 sdmmc registers Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` [PATCH V2 26/27] mmc: mmci: add DT bindings for STM32 sdmmc Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-25 15:27 ` Rob Herring
2018-09-25 15:27 ` Rob Herring
2018-10-01 9:30 ` Ulf Hansson
2018-10-01 9:30 ` Ulf Hansson
2018-09-21 9:46 ` [PATCH V2 27/27] mmc: mmci: add stm32 sdmmc variant Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-09-21 9:46 ` Ludovic Barre
2018-10-01 9:31 ` Ulf Hansson
2018-10-01 9:31 ` Ulf Hansson
2018-10-01 12:56 ` Ludovic BARRE
2018-10-01 12:56 ` Ludovic BARRE
2018-10-01 12:56 ` Ludovic BARRE
2018-10-01 13:39 ` Ulf Hansson
2018-10-01 13:39 ` Ulf Hansson
2018-10-01 13:53 ` Ludovic BARRE
2018-10-01 13:53 ` Ludovic BARRE
2018-10-01 13:53 ` Ludovic BARRE
-- strict thread matches above, loose matches on Subject: below --
2018-09-18 10:55 [PATCH V2 00/27] mmc: mmci: add sdmmc variant for stm32 Ludovic Barre
2018-09-18 10:55 ` [PATCH V2 25/27] mmc: mmci: add stm32 sdmmc registers Ludovic Barre
2018-09-18 10:55 ` Ludovic Barre
2018-09-18 10:55 ` Ludovic Barre
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