From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, kyarlagadda@nvidia.com Cc: ldewangan@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH V3 0/9] bug fixes and more features to Tegra SPI Date: Mon, 15 Apr 2019 14:30:25 -0700 [thread overview] Message-ID: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> (raw) [V3] : This patch series version includes - only patches that are not applied from V2. - splitted expanding mode and adding LSByte First support in separate patches and removed DT property for selecting LSByte First. - Updated GPIO based chip select control to use spi_set_cs from SPI core. - HW based chip select implementation is same as V2 but V3 has this patch updated to be on top of above changes. - HW CS timing implementation is same as V2 but V3 has this patch updated to be on top of above changes. - support for TX and RX trimmers implementation is same as V2 but V3 has this patch updated to be on top of above changes and updated commit description. [V2] : This patch series version includes - only patches that are not applied from V1. - changed order of patches to include all fixes prior to new features support. - Removed HW CS timing from DT properties and created set_cs_timing SPI master optional method for SPI controllers to implement and created API spi_cs_timing for SPI client drivers to request CS setup, hold and inactive delay timing configuration. - Fixed HW based CS decision to be based on single transfer and cs_change. Remove selection of HW based CS through DT. Sowjanya Komatineni (9): spi: tegra114: fix PIO transfer spi: expand mode support spi: add SPI_LSBYTE_FIRST mode spi: tegra114: add support for Tegra SPI LSBYTE_FIRST spi: export spi core function spi_set_cs spi: tegra114: add support for gpio based CS spi: tegra114: add support for hw based cs spi: tegra114: add support for HW CS timing spi: tegra114: add support for TX and RX trimmers drivers/spi/spi-tegra114.c | 175 ++++++++++++++++++++++++++++++++++++++++----- drivers/spi/spi.c | 21 +++--- include/linux/spi/spi.h | 8 ++- 3 files changed, 174 insertions(+), 30 deletions(-) -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com> Cc: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V3 0/9] bug fixes and more features to Tegra SPI Date: Mon, 15 Apr 2019 14:30:25 -0700 [thread overview] Message-ID: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> (raw) [V3] : This patch series version includes - only patches that are not applied from V2. - splitted expanding mode and adding LSByte First support in separate patches and removed DT property for selecting LSByte First. - Updated GPIO based chip select control to use spi_set_cs from SPI core. - HW based chip select implementation is same as V2 but V3 has this patch updated to be on top of above changes. - HW CS timing implementation is same as V2 but V3 has this patch updated to be on top of above changes. - support for TX and RX trimmers implementation is same as V2 but V3 has this patch updated to be on top of above changes and updated commit description. [V2] : This patch series version includes - only patches that are not applied from V1. - changed order of patches to include all fixes prior to new features support. - Removed HW CS timing from DT properties and created set_cs_timing SPI master optional method for SPI controllers to implement and created API spi_cs_timing for SPI client drivers to request CS setup, hold and inactive delay timing configuration. - Fixed HW based CS decision to be based on single transfer and cs_change. Remove selection of HW based CS through DT. Sowjanya Komatineni (9): spi: tegra114: fix PIO transfer spi: expand mode support spi: add SPI_LSBYTE_FIRST mode spi: tegra114: add support for Tegra SPI LSBYTE_FIRST spi: export spi core function spi_set_cs spi: tegra114: add support for gpio based CS spi: tegra114: add support for hw based cs spi: tegra114: add support for HW CS timing spi: tegra114: add support for TX and RX trimmers drivers/spi/spi-tegra114.c | 175 ++++++++++++++++++++++++++++++++++++++++----- drivers/spi/spi.c | 21 +++--- include/linux/spi/spi.h | 8 ++- 3 files changed, 174 insertions(+), 30 deletions(-) -- 2.7.4
next reply other threads:[~2019-04-15 21:30 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-15 21:30 Sowjanya Komatineni [this message] 2019-04-15 21:30 ` [PATCH V3 0/9] bug fixes and more features to Tegra SPI Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 1/9] spi: tegra114: fix PIO transfer Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-16 16:32 ` Applied "spi: tegra114: fix PIO transfer" to the spi tree Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-29 21:42 ` Sowjanya Komatineni 2019-05-02 2:42 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 2/9] spi: expand mode support Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-18 10:26 ` Applied "spi: expand mode support" to the spi tree Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-19 15:22 ` Mark Brown 2019-04-27 0:32 ` Sowjanya Komatineni 2019-05-06 4:49 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 4/9] spi: tegra114: add support for Tegra SPI LSBYTE_FIRST Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 5/9] spi: export spi core function spi_set_cs Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-19 15:18 ` Mark Brown 2019-04-29 22:02 ` Sowjanya Komatineni 2019-05-06 4:44 ` Mark Brown 2019-05-10 18:53 ` Sowjanya Komatineni 2019-05-12 3:12 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 6/9] spi: tegra114: add support for gpio based CS Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 7/9] spi: tegra114: add support for hw based cs Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 8/9] spi: tegra114: add support for HW CS timing Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 9/9] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1555363834-32155-1-git-send-email-skomatineni@nvidia.com \ --to=skomatineni@nvidia.com \ --cc=broonie@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=jonathanh@nvidia.com \ --cc=kyarlagadda@nvidia.com \ --cc=ldewangan@nvidia.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=robh+dt@kernel.org \ --cc=talho@nvidia.com \ --cc=thierry.reding@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.