From: "tip-bot2 for H. Peter Anvin (Intel)" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "H. Peter Anvin (Intel)" <hpa@zytor.com>,
Xin Li <xin3.li@intel.com>, Ingo Molnar <mingo@kernel.org>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] x86/gsseg: Make asm_load_gs_index() take an u16
Date: Thu, 12 Jan 2023 12:16:32 -0000 [thread overview]
Message-ID: <167352579295.4906.1690898852505380960.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20230112072032.35626-4-xin3.li@intel.com>
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: df729fb05ae2db52f7de150439392a88ee9d9b4f
Gitweb: https://git.kernel.org/tip/df729fb05ae2db52f7de150439392a88ee9d9b4f
Author: H. Peter Anvin (Intel) <hpa@zytor.com>
AuthorDate: Wed, 11 Jan 2023 23:20:30 -08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 12 Jan 2023 13:06:36 +01:00
x86/gsseg: Make asm_load_gs_index() take an u16
Let GCC know that only the low 16 bits of load_gs_index() argument
actually matter. It might allow it to create slightly better
code. However, do not propagate this into the prototypes of functions
that end up being paravirtualized, to avoid unnecessary changes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230112072032.35626-4-xin3.li@intel.com
---
arch/x86/entry/entry_64.S | 2 +-
arch/x86/include/asm/special_insns.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 15739a2..7ecd2ae 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -782,7 +782,7 @@ _ASM_NOKPROBE(common_interrupt_return)
/*
* Reload gs selector with exception handling
- * edi: new selector
+ * di: new selector
*
* Is in entry.text as it shouldn't be instrumented.
*/
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 35f709f..a71d0e8 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -120,7 +120,7 @@ static inline void native_wbinvd(void)
asm volatile("wbinvd": : :"memory");
}
-extern asmlinkage void asm_load_gs_index(unsigned int selector);
+extern asmlinkage void asm_load_gs_index(u16 selector);
static inline void native_load_gs_index(unsigned int selector)
{
next prev parent reply other threads:[~2023-01-12 12:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 7:20 [PATCH v6 0/5] x86: Enable LKGS instruction Xin Li
2023-01-12 7:20 ` [PATCH v6 1/5] x86/cpufeature: add the cpu feature bit for LKGS Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/cpufeature: Add the CPU " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/opcode: Add " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Xin Li
2023-01-12 12:16 ` tip-bot2 for H. Peter Anvin (Intel) [this message]
2023-01-12 7:20 ` [PATCH v6 4/5] x86/gsseg: move load_gs_index() to its own new header file Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/gsseg: Move " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Xin Li
2023-01-13 9:36 ` [tip: x86/cpu] x86/gsseg: Use " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 12:13 ` [PATCH v6 0/5] x86: Enable LKGS instruction Ingo Molnar
2023-01-12 14:57 ` Peter Zijlstra
2023-01-13 13:29 ` Ingo Molnar
2023-01-13 18:26 ` Li, Xin3
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