From: Xin Li <xin3.li@intel.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org,
brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com
Subject: [PATCH v6 4/5] x86/gsseg: move load_gs_index() to its own new header file
Date: Wed, 11 Jan 2023 23:20:31 -0800 [thread overview]
Message-ID: <20230112072032.35626-5-xin3.li@intel.com> (raw)
In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com>
From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
GS is a special segment on x86_64, move load_gs_index() to its own new
header file to simplify header inclusion.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---
arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++
arch/x86/include/asm/mmu_context.h | 1 +
arch/x86/include/asm/special_insns.h | 21 --------------
arch/x86/kernel/paravirt.c | 1 +
arch/x86/kernel/signal_32.c | 1 +
arch/x86/kernel/tls.c | 1 +
6 files changed, 45 insertions(+), 21 deletions(-)
create mode 100644 arch/x86/include/asm/gsseg.h
diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h
new file mode 100644
index 000000000000..d15577c39e8d
--- /dev/null
+++ b/arch/x86/include/asm/gsseg.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _ASM_X86_GSSEG_H
+#define _ASM_X86_GSSEG_H
+
+#include <linux/types.h>
+
+#include <asm/asm.h>
+#include <asm/cpufeature.h>
+#include <asm/alternative.h>
+#include <asm/processor.h>
+#include <asm/nops.h>
+
+#ifdef CONFIG_X86_64
+
+extern asmlinkage void asm_load_gs_index(u16 selector);
+
+static inline void native_load_gs_index(unsigned int selector)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ asm_load_gs_index(selector);
+ local_irq_restore(flags);
+}
+
+#endif /* CONFIG_X86_64 */
+
+#ifndef CONFIG_PARAVIRT_XXL
+
+static inline void load_gs_index(unsigned int selector)
+{
+#ifdef CONFIG_X86_64
+ native_load_gs_index(selector);
+#else
+ loadsegment(gs, selector);
+#endif
+}
+
+#endif /* CONFIG_PARAVIRT_XXL */
+
+#endif /* _ASM_X86_GSSEG_H */
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index b8d40ddeab00..e01aa74a6de7 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -12,6 +12,7 @@
#include <asm/tlbflush.h>
#include <asm/paravirt.h>
#include <asm/debugreg.h>
+#include <asm/gsseg.h>
extern atomic64_t last_mm_ctx_id;
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index a71d0e8d4684..cfd9499b617c 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -120,17 +120,6 @@ static inline void native_wbinvd(void)
asm volatile("wbinvd": : :"memory");
}
-extern asmlinkage void asm_load_gs_index(u16 selector);
-
-static inline void native_load_gs_index(unsigned int selector)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- asm_load_gs_index(selector);
- local_irq_restore(flags);
-}
-
static inline unsigned long __read_cr4(void)
{
return native_read_cr4();
@@ -184,16 +173,6 @@ static inline void wbinvd(void)
native_wbinvd();
}
-
-static inline void load_gs_index(unsigned int selector)
-{
-#ifdef CONFIG_X86_64
- native_load_gs_index(selector);
-#else
- loadsegment(gs, selector);
-#endif
-}
-
#endif /* CONFIG_PARAVIRT_XXL */
static inline void clflush(volatile void *__p)
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 327757afb027..bdc886c3f13a 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -32,6 +32,7 @@
#include <asm/special_insns.h>
#include <asm/tlb.h>
#include <asm/io_bitmap.h>
+#include <asm/gsseg.h>
/*
* nop stub, which must not clobber anything *including the stack* to
diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c
index 2553136cf39b..bb4f3f3b1c84 100644
--- a/arch/x86/kernel/signal_32.c
+++ b/arch/x86/kernel/signal_32.c
@@ -31,6 +31,7 @@
#include <asm/sigframe.h>
#include <asm/sighandling.h>
#include <asm/smap.h>
+#include <asm/gsseg.h>
#ifdef CONFIG_IA32_EMULATION
#include <asm/ia32_unistd.h>
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index 3c883e064242..3ffbab0081f4 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -12,6 +12,7 @@
#include <asm/ldt.h>
#include <asm/processor.h>
#include <asm/proto.h>
+#include <asm/gsseg.h>
#include "tls.h"
--
2.34.1
next prev parent reply other threads:[~2023-01-12 7:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 7:20 [PATCH v6 0/5] x86: Enable LKGS instruction Xin Li
2023-01-12 7:20 ` [PATCH v6 1/5] x86/cpufeature: add the cpu feature bit for LKGS Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/cpufeature: Add the CPU " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/opcode: Add " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Xin Li
2023-01-12 12:16 ` [tip: x86/cpu] x86/gsseg: Make " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` Xin Li [this message]
2023-01-12 12:16 ` [tip: x86/cpu] x86/gsseg: Move load_gs_index() to its own new header file tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 7:20 ` [PATCH v6 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Xin Li
2023-01-13 9:36 ` [tip: x86/cpu] x86/gsseg: Use " tip-bot2 for H. Peter Anvin (Intel)
2023-01-12 12:13 ` [PATCH v6 0/5] x86: Enable LKGS instruction Ingo Molnar
2023-01-12 14:57 ` Peter Zijlstra
2023-01-13 13:29 ` Ingo Molnar
2023-01-13 18:26 ` Li, Xin3
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