RE: [PATCH v6 0/5] x86: Enable LKGS instruction

From: "Li, Xin3" <xin3.li@intel.com>
To: Ingo Molnar <mingo@kernel.org>, Peter Zijlstra <peterz@infradead.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"bp@alien8.de" <bp@alien8.de>,
	"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"brgerst@gmail.com" <brgerst@gmail.com>,
	"Bae, Chang Seok" <chang.seok.bae@intel.com>,
	"Gross, Jurgen" <jgross@suse.com>
Subject: RE: [PATCH v6 0/5] x86: Enable LKGS instruction
Date: Fri, 13 Jan 2023 18:26:16 +0000	[thread overview]
Message-ID: <SA1PR11MB6734571ED95606FD753D0A4AA8C29@SA1PR11MB6734.namprd11.prod.outlook.com> (raw)
In-Reply-To: <Y8Fcum+SkeQB9B4H@gmail.com>

> > > > LKGS instruction is introduced with Intel FRED (flexible return
> > > > and event delivery) specification. As LKGS is independent of FRED,
> > > > we enable it as a standalone CPU feature.
> > > >
> > > > LKGS behaves like the MOV to GS instruction except that it loads
> > > > the base address into the IA32_KERNEL_GS_BASE MSR instead of the
> > > > GS segment’s descriptor cache, which is exactly what Linux kernel
> > > > does to load user level GS base.  Thus, with LKGS, there is no
> > > > need to SWAPGS away from the kernel GS base.
> > >
> > > Ok, this looks good to me.
> > >
> > > I've applied the first 4 patches to tip:x86/cpu, as the instruction
> > > exists in a public document and these patches are fine stand-alone
> > > as well, such as the factoring out of load_gs_index() methods from a
> > > high-use low level header into a new header file.
> > >
> > > Planning to apply the final, LKGS enabler patch as well, unless
> > > there's any objections from others?
> >
> > Nah, I think that thing's bike-shedded to near death. Let's just do it.
> 
> Ok - applied the #5 patch to tip:x86/cpu, for a v6.3 merge.
> 
> Thanks,
> 
> 	Ingo

Thanks a lot!
Xin