All of lore.kernel.org
 help / color / mirror / Atom feed
From: "tip-bot2 for Anup Patel" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Anup Patel <apatel@ventanamicro.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: irq/msi] irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure
Date: Fri, 23 Feb 2024 09:43:54 -0000	[thread overview]
Message-ID: <170868143492.398.585451758085811485.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20240222094006.1030709-6-apatel@ventanamicro.com>

The following commit has been merged into the irq/msi branch of tip:

Commit-ID:     a15587277a246c388c83b1cd9cf7c1a868cd752f
Gitweb:        https://git.kernel.org/tip/a15587277a246c388c83b1cd9cf7c1a868cd752f
Author:        Anup Patel <apatel@ventanamicro.com>
AuthorDate:    Thu, 22 Feb 2024 15:09:53 +05:30
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 23 Feb 2024 10:18:44 +01:00

irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure

The SiFive PLIC contexts should not be left dangling if irqdomain creation
fails because plic_starting_cpu() can crash accessing unmapped registers.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240222094006.1030709-6-apatel@ventanamicro.com

---
 drivers/irqchip/irq-sifive-plic.c | 73 +++++++++++++++++++++---------
 1 file changed, 53 insertions(+), 20 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 208fad7..a399cb3 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -417,17 +417,45 @@ static const struct of_device_id plic_match[] = {
 	{}
 };
 
+static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
+				     u32 *parent_hwirq, int *parent_cpu)
+{
+	struct device *dev = &pdev->dev;
+	struct of_phandle_args parent;
+	unsigned long hartid;
+	int rc;
+
+	/*
+	 * Currently, only OF fwnode is supported so extend this
+	 * function for ACPI support.
+	 */
+	if (!is_of_node(dev->fwnode))
+		return -EINVAL;
+
+	rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
+	if (rc)
+		return rc;
+
+	rc = riscv_of_parent_hartid(parent.np, &hartid);
+	if (rc)
+		return rc;
+
+	*parent_hwirq = parent.args[0];
+	*parent_cpu = riscv_hartid_to_cpuid(hartid);
+	return 0;
+}
+
 static int plic_probe(struct platform_device *pdev)
 {
-	int error = 0, nr_contexts, nr_handlers = 0, i;
+	int error = 0, nr_contexts, nr_handlers = 0, cpu, i;
 	struct device *dev = &pdev->dev;
 	unsigned long plic_quirks = 0;
 	struct plic_handler *handler;
+	u32 nr_irqs, parent_hwirq;
 	struct irq_domain *domain;
 	struct plic_priv *priv;
+	irq_hw_number_t hwirq;
 	bool cpuhp_setup;
-	unsigned int cpu;
-	u32 nr_irqs;
 
 	if (is_of_node(dev->fwnode)) {
 		const struct of_device_id *id;
@@ -463,13 +491,9 @@ static int plic_probe(struct platform_device *pdev)
 		return -EINVAL;
 
 	for (i = 0; i < nr_contexts; i++) {
-		struct of_phandle_args parent;
-		irq_hw_number_t hwirq;
-		int cpu;
-		unsigned long hartid;
-
-		if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) {
-			dev_err(dev, "failed to parse parent for context %d.\n", i);
+		error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
+		if (error) {
+			dev_warn(dev, "hwirq for context%d not found\n", i);
 			continue;
 		}
 
@@ -477,7 +501,7 @@ static int plic_probe(struct platform_device *pdev)
 		 * Skip contexts other than external interrupts for our
 		 * privilege level.
 		 */
-		if (parent.args[0] != RV_IRQ_EXT) {
+		if (parent_hwirq != RV_IRQ_EXT) {
 			/* Disable S-mode enable bits if running in M-mode. */
 			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
 				void __iomem *enable_base = priv->regs +
@@ -490,13 +514,6 @@ static int plic_probe(struct platform_device *pdev)
 			continue;
 		}
 
-		error = riscv_of_parent_hartid(parent.np, &hartid);
-		if (error < 0) {
-			dev_warn(dev, "failed to parse hart ID for context %d.\n", i);
-			continue;
-		}
-
-		cpu = riscv_hartid_to_cpuid(hartid);
 		if (cpu < 0) {
 			dev_warn(dev, "Invalid cpuid for context %d\n", i);
 			continue;
@@ -534,7 +551,7 @@ static int plic_probe(struct platform_device *pdev)
 		handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
 						    sizeof(*handler->enable_save), GFP_KERNEL);
 		if (!handler->enable_save)
-			return -ENOMEM;
+			goto fail_cleanup_contexts;
 done:
 		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
 			plic_toggle(handler, hwirq, 0);
@@ -547,7 +564,7 @@ done:
 	priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
 						&plic_irqdomain_ops, priv);
 	if (WARN_ON(!priv->irqdomain))
-		return -ENOMEM;
+		goto fail_cleanup_contexts;
 
 	/*
 	 * We can have multiple PLIC instances so setup cpuhp state
@@ -575,6 +592,22 @@ done:
 	dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
 		 nr_irqs, nr_handlers, nr_contexts);
 	return 0;
+
+fail_cleanup_contexts:
+	for (i = 0; i < nr_contexts; i++) {
+		if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu))
+			continue;
+		if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
+			continue;
+
+		handler = per_cpu_ptr(&plic_handlers, cpu);
+		handler->present = false;
+		handler->hart_base = NULL;
+		handler->enable_base = NULL;
+		handler->enable_save = NULL;
+		handler->priv = NULL;
+	}
+	return -ENOMEM;
 }
 
 static struct platform_driver plic_driver = {

  reply	other threads:[~2024-02-23  9:44 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-22  9:39 [PATCH v14 00/18] Linux RISC-V AIA Support Anup Patel
2024-02-22  9:39 ` Anup Patel
2024-02-22  9:39 ` Anup Patel
2024-02-22  9:39 ` [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-04-03  8:29   ` [PATCH v14 01/18] " Lad, Prabhakar
2024-04-03  8:29     ` Lad, Prabhakar
2024-04-03  8:29     ` Lad, Prabhakar
2024-04-03 14:16     ` Anup Patel
2024-04-03 14:16       ` Anup Patel
2024-04-03 14:16       ` Anup Patel
2024-04-03 15:49       ` Lad, Prabhakar
2024-04-03 15:49         ` Lad, Prabhakar
2024-04-03 15:49         ` Lad, Prabhakar
2024-04-03 16:28         ` Samuel Holland
2024-04-03 16:28           ` Samuel Holland
2024-04-03 16:28           ` Samuel Holland
2024-04-03 18:10           ` Lad, Prabhakar
2024-04-03 18:10             ` Lad, Prabhakar
2024-04-03 18:10             ` Lad, Prabhakar
2024-04-03 16:42         ` Anup Patel
2024-04-03 16:42           ` Anup Patel
2024-04-03 16:42           ` Anup Patel
2024-04-03 17:19         ` Anup Patel
2024-04-03 17:19           ` Anup Patel
2024-04-03 17:19           ` Anup Patel
2024-02-22  9:39 ` [PATCH v14 02/18] irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz() Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 03/18] irqchip/sifive-plic: Use devm_xyz() for managed allocation Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 04/18] irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 05/18] irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` tip-bot2 for Anup Patel [this message]
2024-02-22  9:39 ` [PATCH v14 06/18] irqchip/sifive-plic: Parse number of irqs and contexts early in plic_probe Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe() tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 07/18] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 08/18] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Anup Patel
2024-02-22  9:39 ` [PATCH v14 09/18] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39 ` [PATCH v14 10/18] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Björn Töpel
2024-02-22  9:39 ` [PATCH v14 11/18] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22  9:39   ` Anup Patel
2024-02-22 13:13   ` Björn Töpel
2024-02-22 13:13     ` Björn Töpel
2024-02-22 13:13     ` Björn Töpel
2024-02-22 13:42     ` Anup Patel
2024-02-22 13:42       ` Anup Patel
2024-02-22 13:42       ` Anup Patel
2024-02-22 14:15       ` Björn Töpel
2024-02-22 14:15         ` Björn Töpel
2024-02-22 14:15         ` Björn Töpel
2024-02-23  8:28   ` Thomas Gleixner
2024-02-23  8:28     ` Thomas Gleixner
2024-02-23  8:28     ` Thomas Gleixner
2024-02-23  9:52     ` Anup Patel
2024-02-23  9:52       ` Anup Patel
2024-02-23  9:52       ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 12/18] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22 13:15   ` Björn Töpel
2024-02-22 13:15     ` Björn Töpel
2024-02-22 13:15     ` Björn Töpel
2024-02-22 13:44     ` Anup Patel
2024-02-22 13:44       ` Anup Patel
2024-02-22 13:44       ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 13/18] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22 13:14   ` Björn Töpel
2024-02-22 13:14     ` Björn Töpel
2024-02-22 13:14     ` Björn Töpel
2024-02-22 13:30     ` Anup Patel
2024-02-22 13:30       ` Anup Patel
2024-02-22 13:30       ` Anup Patel
2024-02-22 14:05       ` Björn Töpel
2024-02-22 14:05         ` Björn Töpel
2024-02-22 14:05         ` Björn Töpel
2024-02-22  9:40 ` [PATCH v14 14/18] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 15/18] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 16/18] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 17/18] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 18/18] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-02-22  9:40   ` Anup Patel
2024-02-22  9:40   ` Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=170868143492.398.585451758085811485.tip-bot2@tip-bot2 \
    --to=tip-bot2@linutronix.de \
    --cc=apatel@ventanamicro.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-tip-commits@vger.kernel.org \
    --cc=tglx@linutronix.de \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.