From: Sascha Hauer <s.hauer@pengutronix.de>
To: James Liao <jamesjj.liao@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Heiko Stubner <heiko@sntech.de>,
devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
linux-kernel@vger.kernel.org, Daniel Kurtz <djkurtz@chromium.org>,
Ricky Liang <jcliang@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Sascha Hauer <kernel@pengutronix.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks
Date: Thu, 6 Aug 2015 10:59:36 +0200 [thread overview]
Message-ID: <20150806085936.GO18700@pengutronix.de> (raw)
In-Reply-To: <1438850132.27884.17.camel@mtksdaap41>
On Thu, Aug 06, 2015 at 04:35:32PM +0800, James Liao wrote:
> Hi Sascha,
>
> On Wed, 2015-08-05 at 08:53 +0200, Sascha Hauer wrote:
> > On Tue, Aug 04, 2015 at 04:16:54PM +0800, James Liao wrote:
> > > -static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
> > > - FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
> > > +static const struct mtk_fixed_clk fixed_clks[] __initconst = {
> > > + FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
> > > + FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
> >
> > Hm, it seems you hide PLLs in fixed factor clock. Are you sure that
> > there is a PLL in the system generating 125MHz from 26MHz which is in no
> > way configurable? Or is this really some clock derived from the syspll
> > as the clock name suggests?
>
> According to the datasheet from our clock designer, usb_syspll_125m is
> the output clock of an analog macro which is named SSUSB_PHY, and its
> input clock is AD_CLK26M_CK.
>
> SSUSB_PHY is not the same as general PLLs such as MAINPLL. So I don't
> treat it as a configurable PLL but a fixed clock with the typical rate
> 125 MHz.
Ok then.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
WARNING: multiple messages have this Message-ID (diff)
From: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
To: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Cc: Matthias Brugger
<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Heiko Stubner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Ricky Liang <jcliang-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v6 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks
Date: Thu, 6 Aug 2015 10:59:36 +0200 [thread overview]
Message-ID: <20150806085936.GO18700@pengutronix.de> (raw)
In-Reply-To: <1438850132.27884.17.camel@mtksdaap41>
On Thu, Aug 06, 2015 at 04:35:32PM +0800, James Liao wrote:
> Hi Sascha,
>
> On Wed, 2015-08-05 at 08:53 +0200, Sascha Hauer wrote:
> > On Tue, Aug 04, 2015 at 04:16:54PM +0800, James Liao wrote:
> > > -static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
> > > - FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
> > > +static const struct mtk_fixed_clk fixed_clks[] __initconst = {
> > > + FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
> > > + FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
> >
> > Hm, it seems you hide PLLs in fixed factor clock. Are you sure that
> > there is a PLL in the system generating 125MHz from 26MHz which is in no
> > way configurable? Or is this really some clock derived from the syspll
> > as the clock name suggests?
>
> According to the datasheet from our clock designer, usb_syspll_125m is
> the output clock of an analog macro which is named SSUSB_PHY, and its
> input clock is AD_CLK26M_CK.
>
> SSUSB_PHY is not the same as general PLLs such as MAINPLL. So I don't
> treat it as a configurable PLL but a fixed clock with the typical rate
> 125 MHz.
Ok then.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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WARNING: multiple messages have this Message-ID (diff)
From: s.hauer@pengutronix.de (Sascha Hauer)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks
Date: Thu, 6 Aug 2015 10:59:36 +0200 [thread overview]
Message-ID: <20150806085936.GO18700@pengutronix.de> (raw)
In-Reply-To: <1438850132.27884.17.camel@mtksdaap41>
On Thu, Aug 06, 2015 at 04:35:32PM +0800, James Liao wrote:
> Hi Sascha,
>
> On Wed, 2015-08-05 at 08:53 +0200, Sascha Hauer wrote:
> > On Tue, Aug 04, 2015 at 04:16:54PM +0800, James Liao wrote:
> > > -static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
> > > - FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
> > > - FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
> > > +static const struct mtk_fixed_clk fixed_clks[] __initconst = {
> > > + FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
> > > + FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
> >
> > Hm, it seems you hide PLLs in fixed factor clock. Are you sure that
> > there is a PLL in the system generating 125MHz from 26MHz which is in no
> > way configurable? Or is this really some clock derived from the syspll
> > as the clock name suggests?
>
> According to the datasheet from our clock designer, usb_syspll_125m is
> the output clock of an analog macro which is named SSUSB_PHY, and its
> input clock is AD_CLK26M_CK.
>
> SSUSB_PHY is not the same as general PLLs such as MAINPLL. So I don't
> treat it as a configurable PLL but a fixed clock with the typical rate
> 125 MHz.
Ok then.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
next prev parent reply other threads:[~2015-08-06 8:59 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-04 8:16 [PATCH v6 0/9] Fixes and new clocks support for Mediatek MT8173 James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 1/9] clk: mediatek: Removed unused dpi_ck clock from MT8173 James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 2/9] clk: mediatek: Remove unused code " James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 3/9] clk: mediatek: Add __initdata and __init for data and functions James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 4/9] clk: mediatek: Add fixed clocks support for Mediatek SoC James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-05 6:53 ` Sascha Hauer
2015-08-05 6:53 ` Sascha Hauer
2015-08-05 6:53 ` Sascha Hauer
2015-08-06 8:35 ` James Liao
2015-08-06 8:35 ` James Liao
2015-08-06 8:35 ` James Liao
2015-08-06 8:59 ` Sascha Hauer [this message]
2015-08-06 8:59 ` Sascha Hauer
2015-08-06 8:59 ` Sascha Hauer
2015-08-04 8:16 ` [PATCH v6 6/9] dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173 James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-05 6:46 ` Sascha Hauer
2015-08-05 6:46 ` Sascha Hauer
2015-08-05 6:46 ` Sascha Hauer
2015-08-05 7:26 ` Daniel Kurtz
2015-08-05 7:26 ` Daniel Kurtz
2015-08-05 7:26 ` Daniel Kurtz
2015-08-05 7:36 ` Sascha Hauer
2015-08-05 7:36 ` Sascha Hauer
2015-08-05 7:36 ` Sascha Hauer
2015-08-05 7:41 ` Daniel Kurtz
2015-08-05 7:41 ` Daniel Kurtz
2015-08-05 7:41 ` Daniel Kurtz
2015-08-05 7:50 ` Sascha Hauer
2015-08-05 7:50 ` Sascha Hauer
2015-08-05 7:50 ` Sascha Hauer
2015-08-05 7:58 ` Daniel Kurtz
2015-08-05 7:58 ` Daniel Kurtz
2015-08-05 7:58 ` Daniel Kurtz
2015-08-06 8:23 ` James Liao
2015-08-06 8:23 ` James Liao
2015-08-06 8:23 ` James Liao
2015-08-06 8:53 ` Sascha Hauer
2015-08-06 8:53 ` Sascha Hauer
2015-08-06 9:00 ` James Liao
2015-08-06 9:00 ` James Liao
2015-08-06 9:00 ` James Liao
2015-08-06 9:13 ` Daniel Kurtz
2015-08-06 9:13 ` Daniel Kurtz
2015-08-06 9:13 ` Daniel Kurtz
2015-08-06 10:20 ` Sascha Hauer
2015-08-06 10:20 ` Sascha Hauer
2015-08-06 10:20 ` Sascha Hauer
2015-08-07 2:20 ` James Liao
2015-08-07 2:20 ` James Liao
2015-08-07 2:20 ` James Liao
2015-08-07 8:05 ` Daniel Kurtz
2015-08-07 8:05 ` Daniel Kurtz
2015-08-07 8:05 ` Daniel Kurtz
2015-08-07 8:06 ` Daniel Kurtz
2015-08-07 8:06 ` Daniel Kurtz
2015-08-07 8:06 ` Daniel Kurtz
2015-08-04 8:16 ` [PATCH v6 8/9] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` [PATCH v6 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 8:16 ` James Liao
2015-08-04 13:46 ` [PATCH v6 0/9] Fixes and new clocks support for Mediatek MT8173 Daniel Kurtz
2015-08-04 13:46 ` Daniel Kurtz
2015-08-04 13:46 ` Daniel Kurtz
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