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From: Daniel Kurtz <djkurtz@chromium.org>
To: James Liao <jamesjj.liao@mediatek.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>,
	"open list:OPEN FIRMWARE AND..." <devicetree@vger.kernel.org>,
	Heiko Stubner <heiko@sntech.de>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	Mike Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Ricky Liang <jcliang@chromium.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Sascha Hauer <kernel@pengutronix.de>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173
Date: Thu, 6 Aug 2015 17:13:21 +0800	[thread overview]
Message-ID: <CAGS+omAAYZyZJ4+eSdu2jmwThvHg1YpVoehui_cqNp4A5fURWg@mail.gmail.com> (raw)
In-Reply-To: <1438851644.27884.21.camel@mtksdaap41>

On Thu, Aug 6, 2015 at 5:00 PM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Sascha,
>
> On Thu, 2015-08-06 at 10:53 +0200, Sascha Hauer wrote:
>> On Thu, Aug 06, 2015 at 04:23:51PM +0800, James Liao wrote:
>> > On Wed, 2015-08-05 at 08:46 +0200, Sascha Hauer wrote:
>> > > On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
>> > > >  static const struct mtk_fixed_clk fixed_clks[] __initconst = {
>> > > >         FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
>> > > >         FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", 148.5 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", 51.975 * MHZ),
>> > >
>> > > I would expect 51975 * KHZ here to avoid fractional numbers. Probably
>> > > gcc calculates that during compile time so this will work as expected,
>> > > still I'm not sure this is good style to use fractional numbers here.
>> >
>> > As I know all constants will be calculated in compile time, so there
>> > should be no difference between 51.975 * MHZ and 51975 * KHz.
>> >
>> > > Anyway, on my system lvdspll is running at 150MHz. Are you sure there is
>> > > a clock derived from this running at 148.5MHz? Is it really correct to
>> > > use a fixed clock here or should it rather be lvdspll directly?
>> >
>> > Here is the clock hierarchy between lvdspll and lvds_pxl:
>> >
>> >             --------       AD_VPLL_DPIX_CK  --------   lvds_pxl  -----
>> >            |        |--------------------->|        |---------->|
>> >            |        |                      | cksys  |           |
>> > LVDSPLL -->| LVDSTX |                      | buffer |           | MMSYS
>> >            |        | AD_LVDSTX_CLKDIG_CTS | test   |  lvds_cts |
>> >            |        |--------------------->|        |---------->|
>> >             --------                        --------             -----
>> >
>> > Some clocks and blocks are not modeled into CCF. But we prefer to enable
>> > lvdspll before enabling lvds_pxl. So I modeled lvds_pxl (and lvds_cts)
>> > as a fixed-rate clock with a source from lvdspll.
>> >
>> > The frequency of these fixed-rate clocks (such as 148.5 MHz) are typical
>> > rate. In fact, we don't care about the actual rate of these clocks. We
>> > just care about the enable / disable sequence of them.
>>
>> Please either use the real rate or 0 (along with a explaining why). Using
>> a frequency with four to five significant digits makes me think that the
>> actual rate is very important.
>
> Oops, your suggestion is much different from Daniel's.
>
> Daniel, could you help to comment about how we model these clocks?

First of all, for clocks where the rate doesn't matter, it doesn't
matters to what rate we set the clock.

As for the color of our shed, "the designer says these are the typical
rates" sounds good enough to me for a "real rate", so I prefer using
the rates in James' patch.

If not sure what Sascha's concern is, but if he insists on 0, I'm fine
with that too.

-Dan

WARNING: multiple messages have this Message-ID (diff)
From: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
To: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Cc: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
	"open list:OPEN FIRMWARE AND..."
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Heiko Stubner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
	srv_heupstream
	<srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
	Mike Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Ricky Liang <jcliang-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
	Matthias Brugger
	<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173
Date: Thu, 6 Aug 2015 17:13:21 +0800	[thread overview]
Message-ID: <CAGS+omAAYZyZJ4+eSdu2jmwThvHg1YpVoehui_cqNp4A5fURWg@mail.gmail.com> (raw)
In-Reply-To: <1438851644.27884.21.camel@mtksdaap41>

On Thu, Aug 6, 2015 at 5:00 PM, James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> Hi Sascha,
>
> On Thu, 2015-08-06 at 10:53 +0200, Sascha Hauer wrote:
>> On Thu, Aug 06, 2015 at 04:23:51PM +0800, James Liao wrote:
>> > On Wed, 2015-08-05 at 08:46 +0200, Sascha Hauer wrote:
>> > > On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
>> > > >  static const struct mtk_fixed_clk fixed_clks[] __initconst = {
>> > > >         FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
>> > > >         FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", 148.5 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", 51.975 * MHZ),
>> > >
>> > > I would expect 51975 * KHZ here to avoid fractional numbers. Probably
>> > > gcc calculates that during compile time so this will work as expected,
>> > > still I'm not sure this is good style to use fractional numbers here.
>> >
>> > As I know all constants will be calculated in compile time, so there
>> > should be no difference between 51.975 * MHZ and 51975 * KHz.
>> >
>> > > Anyway, on my system lvdspll is running at 150MHz. Are you sure there is
>> > > a clock derived from this running at 148.5MHz? Is it really correct to
>> > > use a fixed clock here or should it rather be lvdspll directly?
>> >
>> > Here is the clock hierarchy between lvdspll and lvds_pxl:
>> >
>> >             --------       AD_VPLL_DPIX_CK  --------   lvds_pxl  -----
>> >            |        |--------------------->|        |---------->|
>> >            |        |                      | cksys  |           |
>> > LVDSPLL -->| LVDSTX |                      | buffer |           | MMSYS
>> >            |        | AD_LVDSTX_CLKDIG_CTS | test   |  lvds_cts |
>> >            |        |--------------------->|        |---------->|
>> >             --------                        --------             -----
>> >
>> > Some clocks and blocks are not modeled into CCF. But we prefer to enable
>> > lvdspll before enabling lvds_pxl. So I modeled lvds_pxl (and lvds_cts)
>> > as a fixed-rate clock with a source from lvdspll.
>> >
>> > The frequency of these fixed-rate clocks (such as 148.5 MHz) are typical
>> > rate. In fact, we don't care about the actual rate of these clocks. We
>> > just care about the enable / disable sequence of them.
>>
>> Please either use the real rate or 0 (along with a explaining why). Using
>> a frequency with four to five significant digits makes me think that the
>> actual rate is very important.
>
> Oops, your suggestion is much different from Daniel's.
>
> Daniel, could you help to comment about how we model these clocks?

First of all, for clocks where the rate doesn't matter, it doesn't
matters to what rate we set the clock.

As for the color of our shed, "the designer says these are the typical
rates" sounds good enough to me for a "real rate", so I prefer using
the rates in James' patch.

If not sure what Sascha's concern is, but if he insists on 0, I'm fine
with that too.

-Dan
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WARNING: multiple messages have this Message-ID (diff)
From: djkurtz@chromium.org (Daniel Kurtz)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173
Date: Thu, 6 Aug 2015 17:13:21 +0800	[thread overview]
Message-ID: <CAGS+omAAYZyZJ4+eSdu2jmwThvHg1YpVoehui_cqNp4A5fURWg@mail.gmail.com> (raw)
In-Reply-To: <1438851644.27884.21.camel@mtksdaap41>

On Thu, Aug 6, 2015 at 5:00 PM, James Liao <jamesjj.liao@mediatek.com> wrote:
> Hi Sascha,
>
> On Thu, 2015-08-06 at 10:53 +0200, Sascha Hauer wrote:
>> On Thu, Aug 06, 2015 at 04:23:51PM +0800, James Liao wrote:
>> > On Wed, 2015-08-05 at 08:46 +0200, Sascha Hauer wrote:
>> > > On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
>> > > >  static const struct mtk_fixed_clk fixed_clks[] __initconst = {
>> > > >         FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ),
>> > > >         FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", 130 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", 148.5 * MHZ),
>> > > > +       FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", 51.975 * MHZ),
>> > >
>> > > I would expect 51975 * KHZ here to avoid fractional numbers. Probably
>> > > gcc calculates that during compile time so this will work as expected,
>> > > still I'm not sure this is good style to use fractional numbers here.
>> >
>> > As I know all constants will be calculated in compile time, so there
>> > should be no difference between 51.975 * MHZ and 51975 * KHz.
>> >
>> > > Anyway, on my system lvdspll is running at 150MHz. Are you sure there is
>> > > a clock derived from this running at 148.5MHz? Is it really correct to
>> > > use a fixed clock here or should it rather be lvdspll directly?
>> >
>> > Here is the clock hierarchy between lvdspll and lvds_pxl:
>> >
>> >             --------       AD_VPLL_DPIX_CK  --------   lvds_pxl  -----
>> >            |        |--------------------->|        |---------->|
>> >            |        |                      | cksys  |           |
>> > LVDSPLL -->| LVDSTX |                      | buffer |           | MMSYS
>> >            |        | AD_LVDSTX_CLKDIG_CTS | test   |  lvds_cts |
>> >            |        |--------------------->|        |---------->|
>> >             --------                        --------             -----
>> >
>> > Some clocks and blocks are not modeled into CCF. But we prefer to enable
>> > lvdspll before enabling lvds_pxl. So I modeled lvds_pxl (and lvds_cts)
>> > as a fixed-rate clock with a source from lvdspll.
>> >
>> > The frequency of these fixed-rate clocks (such as 148.5 MHz) are typical
>> > rate. In fact, we don't care about the actual rate of these clocks. We
>> > just care about the enable / disable sequence of them.
>>
>> Please either use the real rate or 0 (along with a explaining why). Using
>> a frequency with four to five significant digits makes me think that the
>> actual rate is very important.
>
> Oops, your suggestion is much different from Daniel's.
>
> Daniel, could you help to comment about how we model these clocks?

First of all, for clocks where the rate doesn't matter, it doesn't
matters to what rate we set the clock.

As for the color of our shed, "the designer says these are the typical
rates" sounds good enough to me for a "real rate", so I prefer using
the rates in James' patch.

If not sure what Sascha's concern is, but if he insists on 0, I'm fine
with that too.

-Dan

  reply	other threads:[~2015-08-06  9:13 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-04  8:16 [PATCH v6 0/9] Fixes and new clocks support for Mediatek MT8173 James Liao
2015-08-04  8:16 ` James Liao
2015-08-04  8:16 ` James Liao
2015-08-04  8:16 ` [PATCH v6 1/9] clk: mediatek: Removed unused dpi_ck clock from MT8173 James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 2/9] clk: mediatek: Remove unused code " James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 3/9] clk: mediatek: Add __initdata and __init for data and functions James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 4/9] clk: mediatek: Add fixed clocks support for Mediatek SoC James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-05  6:53   ` Sascha Hauer
2015-08-05  6:53     ` Sascha Hauer
2015-08-05  6:53     ` Sascha Hauer
2015-08-06  8:35     ` James Liao
2015-08-06  8:35       ` James Liao
2015-08-06  8:35       ` James Liao
2015-08-06  8:59       ` Sascha Hauer
2015-08-06  8:59         ` Sascha Hauer
2015-08-06  8:59         ` Sascha Hauer
2015-08-04  8:16 ` [PATCH v6 6/9] dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173 James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-05  6:46   ` Sascha Hauer
2015-08-05  6:46     ` Sascha Hauer
2015-08-05  6:46     ` Sascha Hauer
2015-08-05  7:26     ` Daniel Kurtz
2015-08-05  7:26       ` Daniel Kurtz
2015-08-05  7:26       ` Daniel Kurtz
2015-08-05  7:36       ` Sascha Hauer
2015-08-05  7:36         ` Sascha Hauer
2015-08-05  7:36         ` Sascha Hauer
2015-08-05  7:41         ` Daniel Kurtz
2015-08-05  7:41           ` Daniel Kurtz
2015-08-05  7:41           ` Daniel Kurtz
2015-08-05  7:50           ` Sascha Hauer
2015-08-05  7:50             ` Sascha Hauer
2015-08-05  7:50             ` Sascha Hauer
2015-08-05  7:58             ` Daniel Kurtz
2015-08-05  7:58               ` Daniel Kurtz
2015-08-05  7:58               ` Daniel Kurtz
2015-08-06  8:23     ` James Liao
2015-08-06  8:23       ` James Liao
2015-08-06  8:23       ` James Liao
2015-08-06  8:53       ` Sascha Hauer
2015-08-06  8:53         ` Sascha Hauer
2015-08-06  9:00         ` James Liao
2015-08-06  9:00           ` James Liao
2015-08-06  9:00           ` James Liao
2015-08-06  9:13           ` Daniel Kurtz [this message]
2015-08-06  9:13             ` Daniel Kurtz
2015-08-06  9:13             ` Daniel Kurtz
2015-08-06 10:20             ` Sascha Hauer
2015-08-06 10:20               ` Sascha Hauer
2015-08-06 10:20               ` Sascha Hauer
2015-08-07  2:20               ` James Liao
2015-08-07  2:20                 ` James Liao
2015-08-07  2:20                 ` James Liao
2015-08-07  8:05                 ` Daniel Kurtz
2015-08-07  8:05                   ` Daniel Kurtz
2015-08-07  8:05                   ` Daniel Kurtz
2015-08-07  8:06                   ` Daniel Kurtz
2015-08-07  8:06                     ` Daniel Kurtz
2015-08-07  8:06                     ` Daniel Kurtz
2015-08-04  8:16 ` [PATCH v6 8/9] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16 ` [PATCH v6 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes James Liao
2015-08-04  8:16   ` James Liao
2015-08-04  8:16   ` James Liao
2015-08-04 13:46 ` [PATCH v6 0/9] Fixes and new clocks support for Mediatek MT8173 Daniel Kurtz
2015-08-04 13:46   ` Daniel Kurtz
2015-08-04 13:46   ` Daniel Kurtz

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