From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes
Date: Fri, 14 Jul 2017 14:42:59 +0800 [thread overview]
Message-ID: <20170714064302.20383-9-wens@csie.org> (raw)
In-Reply-To: <20170714064302.20383-1-wens@csie.org>
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index beed05e10a3b..085312d0c521 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,63 @@
#dma-cells = <1>;
};
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun8i-a83t-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
--
2.13.2
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes
Date: Fri, 14 Jul 2017 14:42:59 +0800 [thread overview]
Message-ID: <20170714064302.20383-9-wens@csie.org> (raw)
In-Reply-To: <20170714064302.20383-1-wens-jdAy2FN1RRM@public.gmane.org>
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index beed05e10a3b..085312d0c521 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,63 @@
#dma-cells = <1>;
};
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun8i-a83t-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
--
2.13.2
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes
Date: Fri, 14 Jul 2017 14:42:59 +0800 [thread overview]
Message-ID: <20170714064302.20383-9-wens@csie.org> (raw)
In-Reply-To: <20170714064302.20383-1-wens@csie.org>
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index beed05e10a3b..085312d0c521 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,63 @@
#dma-cells = <1>;
};
+ mmc0: mmc at 1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc at 1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc at 1c11000 {
+ compatible = "allwinner,sun8i-a83t-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock at 1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
--
2.13.2
next prev parent reply other threads:[~2017-07-14 6:43 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-14 6:42 [PATCH 00/11] ARM: sun8i: a83t: Add support for MMC controllers Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` [PATCH 01/11] ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-17 9:06 ` Maxime Ripard
2017-07-17 9:06 ` Maxime Ripard
2017-07-17 9:06 ` Maxime Ripard
2017-07-14 6:42 ` [PATCH 02/11] clk: sunxi-ng: Add interface to query or configure MMC timing modes Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-17 9:09 ` Maxime Ripard
2017-07-17 9:09 ` Maxime Ripard
2017-07-17 9:09 ` Maxime Ripard
2017-07-14 6:42 ` [PATCH 03/11] clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 10:12 ` Chen-Yu Tsai
2017-07-17 10:12 ` Chen-Yu Tsai
2017-07-17 10:12 ` Chen-Yu Tsai
2017-07-18 14:47 ` Maxime Ripard
2017-07-18 14:47 ` Maxime Ripard
2017-07-14 6:42 ` [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 9:16 ` Ulf Hansson
2017-07-14 9:16 ` Ulf Hansson
2017-07-14 9:16 ` Ulf Hansson
2017-07-14 9:16 ` Ulf Hansson
2017-07-14 9:44 ` Chen-Yu Tsai
2017-07-14 9:44 ` Chen-Yu Tsai
2017-07-14 9:44 ` Chen-Yu Tsai
2017-07-14 9:44 ` Chen-Yu Tsai
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 9:14 ` Maxime Ripard
2017-07-17 10:37 ` Ulf Hansson
2017-07-17 10:37 ` Ulf Hansson
2017-07-17 10:37 ` Ulf Hansson
2017-07-17 10:37 ` Ulf Hansson
2017-07-14 6:42 ` [PATCH 05/11] mmc: sunxi: Support controllers that can use both old and new timings Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 9:26 ` Ulf Hansson
2017-07-14 9:26 ` Ulf Hansson
2017-07-14 9:26 ` Ulf Hansson
2017-07-14 9:26 ` Ulf Hansson
2017-07-14 9:40 ` Chen-Yu Tsai
2017-07-14 9:40 ` Chen-Yu Tsai
2017-07-14 9:40 ` Chen-Yu Tsai
2017-07-14 9:40 ` Chen-Yu Tsai
2017-07-14 9:57 ` Ulf Hansson
2017-07-14 9:57 ` Ulf Hansson
2017-07-14 9:57 ` Ulf Hansson
2017-07-17 9:20 ` Maxime Ripard
2017-07-17 9:20 ` Maxime Ripard
2017-07-17 9:20 ` Maxime Ripard
2017-07-17 9:20 ` Maxime Ripard
2017-07-17 9:17 ` Maxime Ripard
2017-07-17 9:17 ` Maxime Ripard
2017-07-17 9:17 ` Maxime Ripard
2017-07-19 8:59 ` Chen-Yu Tsai
2017-07-19 8:59 ` Chen-Yu Tsai
2017-07-19 8:59 ` Chen-Yu Tsai
2017-07-19 11:28 ` Maxime Ripard
2017-07-19 11:28 ` Maxime Ripard
2017-07-19 11:28 ` Maxime Ripard
2017-07-17 13:10 ` kbuild test robot
2017-07-17 13:10 ` kbuild test robot
2017-07-17 13:10 ` kbuild test robot
2017-07-14 6:42 ` [PATCH 06/11] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` [PATCH 07/11] mmc: sunxi: Add support for A83T eMMC (MMC2) Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-17 18:51 ` Rob Herring
2017-07-17 18:51 ` Rob Herring
2017-07-14 6:42 ` Chen-Yu Tsai [this message]
2017-07-14 6:42 ` [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes Chen-Yu Tsai
2017-07-14 6:42 ` Chen-Yu Tsai
2017-07-17 9:22 ` Maxime Ripard
2017-07-17 9:22 ` Maxime Ripard
2017-07-17 9:22 ` Maxime Ripard
2017-07-14 6:43 ` [PATCH 09/11] ARM: dts: sun8i: a83t: Add pingroup for 8-bit eMMC on mmc2 Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
2017-07-14 6:43 ` [PATCH 10/11] ARM: dts: sun8i: a83t: cubietruck-plus: Enable micro-SD card and eMMC Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
2017-07-14 6:43 ` [PATCH 11/11] ARM: dts: sun8i: a83t: h8homlet: Enable micro-SD card and onboard eMMC Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
2017-07-14 6:43 ` Chen-Yu Tsai
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