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From: Dirk Behme <dirk.behme@de.bosch.com>
To: <linux-renesas-soc@vger.kernel.org>, <linux-spi@vger.kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>,
	Dirk Behme <dirk.behme@de.bosch.com>
Subject: [PATCH 1/8] spi: sh-msiof: Add sleep before master transfer for test
Date: Wed, 6 Sep 2017 09:05:00 +0200	[thread overview]
Message-ID: <20170906070507.26223-2-dirk.behme@de.bosch.com> (raw)
In-Reply-To: <20170906070507.26223-1-dirk.behme@de.bosch.com>

From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>

This patch is for debug of transfer between master and slave.
Since the slave needs to complete a preparation in data transfer
before the master working, the sleep wait is put before
the data transfer of the master.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
---
 drivers/spi/Kconfig        | 20 ++++++++++++++++++++
 drivers/spi/spi-sh-msiof.c | 15 +++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a75f2a2cf780..0139ecf8f42e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -600,6 +600,26 @@ config SPI_SH_MSIOF
 	help
 	  SPI driver for SuperH and SH Mobile MSIOF blocks.
 
+config SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG
+	bool "Transfer Synchronization Debug support for MSIOF"
+	depends on SPI_SH_MSIOF
+	default n
+	help
+	  In data transfer, the slave needs to have completed
+	  a transfer preparation before the master.
+	  As a test environment, it was to be able to put a sleep wait
+	  before the data transfer of the master.
+
+config SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG_MSLEEP
+	int "Master of sleep latency (msec time)"
+	default 1
+	depends on SPI_SH_MSIOF && SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG
+	help
+	  Select Sleep latency of the previous data transfer
+	  at the time of master mode.
+	  Examples:
+	    N => N msec
+
 config SPI_SH
 	tristate "SuperH SPI controller"
 	depends on SUPERH || COMPILE_TEST
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 0eb1e9583485..2b4d3a520176 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -41,6 +41,10 @@ struct sh_msiof_chipdata {
 	u16 min_div;
 };
 
+#ifdef CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG
+#define TRANSFAR_SYNC_DELAY (CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG_MSLEEP)
+#endif /* CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG */
+
 struct sh_msiof_spi_priv {
 	struct spi_master *master;
 	void __iomem *mapbase;
@@ -910,6 +914,11 @@ static int sh_msiof_transfer_one(struct spi_master *master,
 		if (tx_buf)
 			copy32(p->tx_dma_page, tx_buf, l / 4);
 
+#ifdef CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG
+		if (p->mode == SPI_MSIOF_MASTER)
+			msleep(TRANSFAR_SYNC_DELAY);
+#endif /* CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG */
+
 		ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
 		if (ret == -EAGAIN) {
 			pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
@@ -983,6 +992,12 @@ static int sh_msiof_transfer_one(struct spi_master *master,
 	words = len / bytes_per_word;
 
 	while (words > 0) {
+
+#ifdef CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG
+		if (p->mode == SPI_MSIOF_MASTER)
+			msleep(TRANSFAR_SYNC_DELAY);
+#endif /* CONFIG_SPI_SH_MSIOF_TRANSFER_SYNC_DEBUG */
+
 		n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
 					   words, bits);
 		if (n < 0)
-- 
2.14.1

  reply	other threads:[~2017-09-06  7:05 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-06  7:04 [PATCH 0/8] spi: sh-msiof: Import some BSP patches Dirk Behme
2017-09-06  7:05 ` Dirk Behme [this message]
2017-09-07  7:04   ` [PATCH 1/8] spi: sh-msiof: Add sleep before master transfer for test Vladimir Zapolskiy
2017-09-07  7:04     ` Vladimir Zapolskiy
2017-09-07  7:16     ` Dirk Behme
2017-09-07  7:16       ` Dirk Behme
2017-09-07  8:11   ` Geert Uytterhoeven
2017-09-07  8:26     ` Dirk Behme
2017-09-07  8:26       ` Dirk Behme
2017-09-06  7:05 ` [PATCH 2/8] spi: sh-msiof: Fix DMA transfer size check Dirk Behme
2017-09-07  8:31   ` Geert Uytterhoeven
2017-09-07  8:33     ` Dirk Behme
2017-09-07  8:39       ` Geert Uytterhoeven
2017-09-07  8:39         ` Geert Uytterhoeven
2017-09-07  8:42         ` Dirk Behme
2017-09-07  8:59           ` Geert Uytterhoeven
2017-09-07  9:05             ` Dirk Behme
2017-09-07  9:05               ` Dirk Behme
2017-09-07  9:12               ` Geert Uytterhoeven
2017-09-07  9:12                 ` Geert Uytterhoeven
2018-01-03 17:25                 ` Geert Uytterhoeven
2018-01-03 17:25                   ` Geert Uytterhoeven
2018-01-04  7:19                   ` Dirk Behme
2018-01-04  8:24                     ` Geert Uytterhoeven
2017-09-06  7:05 ` [PATCH 3/8] spi: sh-msiof: Fix MSIOF address for DMAC Dirk Behme
2017-09-06  7:05   ` Dirk Behme
2017-09-06  9:22   ` Geert Uytterhoeven
2017-09-06 10:09     ` Dirk Behme
2017-09-06 10:09       ` Dirk Behme
2017-09-06 10:42       ` Geert Uytterhoeven
2017-09-06 10:59         ` Dirk Behme
2017-09-06 10:59           ` Dirk Behme
2017-09-06 11:01           ` Geert Uytterhoeven
2017-09-06  7:05 ` [PATCH 4/8] spi: sh-msiof: Fix DMA completion Dirk Behme
2017-09-07  8:33   ` Geert Uytterhoeven
2017-09-07  8:33     ` Geert Uytterhoeven
2017-09-07  8:41     ` Dirk Behme
2017-09-07  8:41       ` Dirk Behme
2017-09-06  7:05 ` [PATCH 5/8] spi: sh-msiof: Wait for Tx FIFO empty after DMA Dirk Behme
2017-09-06 17:57   ` Sergei Shtylyov
2017-09-07  8:34   ` Geert Uytterhoeven
2017-09-07  8:34     ` Geert Uytterhoeven
2017-09-06  7:05 ` [PATCH 6/8] spi: sh-msiof: Add MSIOF parent clock changing function for R-Car Gen3 Dirk Behme
2017-09-07  8:38   ` Geert Uytterhoeven
2017-09-06  7:05 ` [PATCH 7/8] spi: sh-msiof: Fix gpio function Dirk Behme
2017-09-06  7:05   ` Dirk Behme
2017-09-07  8:24   ` Geert Uytterhoeven
2017-09-06  7:05 ` [PATCH 8/8] spi: sh-msiof: Add registers reset Dirk Behme
2017-09-06  7:05   ` Dirk Behme
2017-09-06 18:11   ` Sergei Shtylyov
2017-09-07  8:11   ` Geert Uytterhoeven
2017-09-07  8:11     ` Geert Uytterhoeven

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