From: Dave Martin <Dave.Martin@arm.com> To: "Alex Bennée" <alex.bennee@linaro.org> Cc: linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>, Szabolcs Nagy <szabolcs.nagy@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Suzuki K Poulose <Suzuki.Poulose@arm.com>, Will Deacon <will.deacon@arm.com>, Richard Sandiford <richard.sandiford@arm.com>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths Date: Thu, 28 Sep 2017 15:22:12 +0100 [thread overview] Message-ID: <20170928142212.GB3611@e103592.cambridge.arm.com> (raw) In-Reply-To: <87fubpaa1o.fsf@linaro.org> On Thu, Sep 14, 2017 at 10:45:07AM +0100, Alex Bennée wrote: > > Dave Martin <Dave.Martin@arm.com> writes: > > > This patch uses the cpufeatures framework to determine common SVE > > capabilities and vector lengths, and configures the runtime SVE > > support code appropriately. > > > > ZCR_ELx is not really a feature register, but it is convenient to > > use it as a template for recording the maximum vector length > > supported by a CPU, using the LEN field. This field is similar to > > a feature field in that it is a contiguous bitfield for which we > > want to determine the minimum system-wide value. This patch adds > > ZCR as a pseudo-register in cpuinfo/cpufeatures, with appropriate > > custom code to populate it. Finding the minimum supported value of > > the LEN field is left to the cpufeatures framework in the usual > > way. > > > > The meaning of ID_AA64ZFR0_EL1 is not architecturally defined yet, > > so for now we just require it to be zero. > > > > Note that much of this code is dormant and SVE still won't be used > > yet, since system_supports_sve() remains hardwired to false. > > > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > > Cc: Alex Bennée <alex.bennee@linaro.org> > > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > > > > --- > > > > Changes since v1 > > ---------------- > > > > Requested by Alex Bennée: > > > > * Thin out BUG_ON()s: > > Redundant BUG_ON()s and ones that just check invariants are removed. > > Important sanity-checks are migrated to WARN_ON()s, with some > > minimal best-effort patch-up code. > > > > Other changes related to Alex Bennée's comments: > > > > * Migrate away from magic numbers for converting VL to VQ. > > > > Requested by Suzuki Poulose: > > > > * Make sve_vq_map __ro_after_init. > > > > Other changes related to Suzuki Poulose's comments: > > > > * Rely on cpufeatures for not attempting to update the vq map after boot. > > --- > > arch/arm64/include/asm/cpu.h | 4 ++ > > arch/arm64/include/asm/cpufeature.h | 29 ++++++++++ > > arch/arm64/include/asm/fpsimd.h | 10 ++++ > > arch/arm64/kernel/cpufeature.c | 50 +++++++++++++++++ > > arch/arm64/kernel/cpuinfo.c | 6 ++ > > arch/arm64/kernel/fpsimd.c | 106 +++++++++++++++++++++++++++++++++++- > > 6 files changed, 202 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index 889226b..8839227 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -41,6 +41,7 @@ struct cpuinfo_arm64 { > > u64 reg_id_aa64mmfr2; > > u64 reg_id_aa64pfr0; > > u64 reg_id_aa64pfr1; > > + u64 reg_id_aa64zfr0; > > > > u32 reg_id_dfr0; > > u32 reg_id_isar0; > > @@ -59,6 +60,9 @@ struct cpuinfo_arm64 { > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > u32 reg_mvfr2; > > + > > + /* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */ > > + u64 reg_zcr; > > }; > > > > DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > > index 4ea3441..d98e7ba 100644 > > --- a/arch/arm64/include/asm/cpufeature.h > > +++ b/arch/arm64/include/asm/cpufeature.h > > @@ -10,7 +10,9 @@ > > #define __ASM_CPUFEATURE_H > > > > #include <asm/cpucaps.h> > > +#include <asm/fpsimd.h> > > #include <asm/hwcap.h> > > +#include <asm/sigcontext.h> > > #include <asm/sysreg.h> > > > > /* > > @@ -223,6 +225,13 @@ static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) > > return val == ID_AA64PFR0_EL0_32BIT_64BIT; > > } > > > > +static inline bool id_aa64pfr0_sve(u64 pfr0) > > +{ > > + u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); > > + > > + return val > 0; > > +} > > + > > void __init setup_cpu_features(void); > > > > void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, > > @@ -267,6 +276,26 @@ static inline bool system_supports_sve(void) > > return false; > > } > > > > +/* > > + * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE > > + * vector length. > > + * Use only if SVE is present. This function clobbers the SVE vector length. > > + */ > > :nit whitespace formatting. I'll add some newlines now to make this cleaner. /* * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE * vector length. * * Use only if SVE is present. * This function clobbers the SVE vector length. */ OK? > > > +static u64 __maybe_unused read_zcr_features(void) > > +{ > > + u64 zcr; > > + unsigned int vq_max; > > + > > + write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); > > I'm confused, why are we writing something here? You mention clobbering > the SVE vector length but what was the point? Hmm, this deserves a comment -- coming back to this code, I had to think about it. Are the following extra comments sufficient explanation? /* * Set the maximum possible VL, and write zeroes to all other * bits to see if they stick. */ write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); zcr = read_sysreg_s(SYS_ZCR_EL1); zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* flag up sticky 1s outside LEN field */ vq_max = sve_vq_from_vl(sve_get_vl()); zcr |= vq_max - 1; /* set LEN field to maximum effective value */ [...] > Otherwise: > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> I'll wait on your responses to the above first. Cheers ---Dave
WARNING: multiple messages have this Message-ID (diff)
From: Dave.Martin@arm.com (Dave Martin) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths Date: Thu, 28 Sep 2017 15:22:12 +0100 [thread overview] Message-ID: <20170928142212.GB3611@e103592.cambridge.arm.com> (raw) In-Reply-To: <87fubpaa1o.fsf@linaro.org> On Thu, Sep 14, 2017 at 10:45:07AM +0100, Alex Benn?e wrote: > > Dave Martin <Dave.Martin@arm.com> writes: > > > This patch uses the cpufeatures framework to determine common SVE > > capabilities and vector lengths, and configures the runtime SVE > > support code appropriately. > > > > ZCR_ELx is not really a feature register, but it is convenient to > > use it as a template for recording the maximum vector length > > supported by a CPU, using the LEN field. This field is similar to > > a feature field in that it is a contiguous bitfield for which we > > want to determine the minimum system-wide value. This patch adds > > ZCR as a pseudo-register in cpuinfo/cpufeatures, with appropriate > > custom code to populate it. Finding the minimum supported value of > > the LEN field is left to the cpufeatures framework in the usual > > way. > > > > The meaning of ID_AA64ZFR0_EL1 is not architecturally defined yet, > > so for now we just require it to be zero. > > > > Note that much of this code is dormant and SVE still won't be used > > yet, since system_supports_sve() remains hardwired to false. > > > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > > Cc: Alex Benn?e <alex.bennee@linaro.org> > > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > > > > --- > > > > Changes since v1 > > ---------------- > > > > Requested by Alex Benn?e: > > > > * Thin out BUG_ON()s: > > Redundant BUG_ON()s and ones that just check invariants are removed. > > Important sanity-checks are migrated to WARN_ON()s, with some > > minimal best-effort patch-up code. > > > > Other changes related to Alex Benn?e's comments: > > > > * Migrate away from magic numbers for converting VL to VQ. > > > > Requested by Suzuki Poulose: > > > > * Make sve_vq_map __ro_after_init. > > > > Other changes related to Suzuki Poulose's comments: > > > > * Rely on cpufeatures for not attempting to update the vq map after boot. > > --- > > arch/arm64/include/asm/cpu.h | 4 ++ > > arch/arm64/include/asm/cpufeature.h | 29 ++++++++++ > > arch/arm64/include/asm/fpsimd.h | 10 ++++ > > arch/arm64/kernel/cpufeature.c | 50 +++++++++++++++++ > > arch/arm64/kernel/cpuinfo.c | 6 ++ > > arch/arm64/kernel/fpsimd.c | 106 +++++++++++++++++++++++++++++++++++- > > 6 files changed, 202 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index 889226b..8839227 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -41,6 +41,7 @@ struct cpuinfo_arm64 { > > u64 reg_id_aa64mmfr2; > > u64 reg_id_aa64pfr0; > > u64 reg_id_aa64pfr1; > > + u64 reg_id_aa64zfr0; > > > > u32 reg_id_dfr0; > > u32 reg_id_isar0; > > @@ -59,6 +60,9 @@ struct cpuinfo_arm64 { > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > u32 reg_mvfr2; > > + > > + /* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */ > > + u64 reg_zcr; > > }; > > > > DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > > index 4ea3441..d98e7ba 100644 > > --- a/arch/arm64/include/asm/cpufeature.h > > +++ b/arch/arm64/include/asm/cpufeature.h > > @@ -10,7 +10,9 @@ > > #define __ASM_CPUFEATURE_H > > > > #include <asm/cpucaps.h> > > +#include <asm/fpsimd.h> > > #include <asm/hwcap.h> > > +#include <asm/sigcontext.h> > > #include <asm/sysreg.h> > > > > /* > > @@ -223,6 +225,13 @@ static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) > > return val == ID_AA64PFR0_EL0_32BIT_64BIT; > > } > > > > +static inline bool id_aa64pfr0_sve(u64 pfr0) > > +{ > > + u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); > > + > > + return val > 0; > > +} > > + > > void __init setup_cpu_features(void); > > > > void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, > > @@ -267,6 +276,26 @@ static inline bool system_supports_sve(void) > > return false; > > } > > > > +/* > > + * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE > > + * vector length. > > + * Use only if SVE is present. This function clobbers the SVE vector length. > > + */ > > :nit whitespace formatting. I'll add some newlines now to make this cleaner. /* * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE * vector length. * * Use only if SVE is present. * This function clobbers the SVE vector length. */ OK? > > > +static u64 __maybe_unused read_zcr_features(void) > > +{ > > + u64 zcr; > > + unsigned int vq_max; > > + > > + write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); > > I'm confused, why are we writing something here? You mention clobbering > the SVE vector length but what was the point? Hmm, this deserves a comment -- coming back to this code, I had to think about it. Are the following extra comments sufficient explanation? /* * Set the maximum possible VL, and write zeroes to all other * bits to see if they stick. */ write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); zcr = read_sysreg_s(SYS_ZCR_EL1); zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* flag up sticky 1s outside LEN field */ vq_max = sve_vq_from_vl(sve_get_vl()); zcr |= vq_max - 1; /* set LEN field to maximum effective value */ [...] > Otherwise: > > Reviewed-by: Alex Benn?e <alex.bennee@linaro.org> I'll wait on your responses to the above first. Cheers ---Dave
next prev parent reply other threads:[~2017-09-28 14:22 UTC|newest] Thread overview: 224+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-31 17:00 [PATCH v2 00/28] ARM Scalable Vector Extension (SVE) Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 01/28] regset: Add support for dynamically sized regsets Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU features from guests Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 14:37 ` Alex Bennée 2017-09-13 14:37 ` Alex Bennée 2017-09-13 14:37 ` Alex Bennée 2017-09-15 0:04 ` Dave Martin 2017-09-15 0:04 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 03/28] arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 04/28] arm64: Port deprecated instruction emulation to new sysctl interface Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 05/28] arm64: fpsimd: Simplify uses of {set,clear}_ti_thread_flag() Dave Martin 2017-08-31 17:00 ` [PATCH v2 05/28] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag() Dave Martin 2017-08-31 17:00 ` [PATCH v2 06/28] arm64/sve: System register and exception syndrome definitions Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 14:48 ` Alex Bennée 2017-09-13 14:48 ` Alex Bennée 2017-09-13 14:48 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 07/28] arm64/sve: Low-level SVE architectural state manipulation functions Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 15:39 ` Alex Bennée 2017-09-13 15:39 ` Alex Bennée 2017-09-13 15:39 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 08/28] arm64/sve: Kconfig update and conditional compilation support Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 09/28] arm64/sve: Signal frame and context structure definition Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 13:36 ` Catalin Marinas 2017-09-13 13:36 ` Catalin Marinas 2017-09-13 21:33 ` Dave Martin 2017-09-13 21:33 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 10/28] arm64/sve: Low-level CPU setup Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 13:32 ` Catalin Marinas 2017-09-13 13:32 ` Catalin Marinas 2017-09-13 19:21 ` Dave Martin 2017-09-13 19:21 ` Dave Martin 2017-09-13 19:21 ` Dave Martin 2017-10-05 10:47 ` Dave Martin 2017-10-05 10:47 ` Dave Martin 2017-10-05 11:04 ` Suzuki K Poulose 2017-10-05 11:04 ` Suzuki K Poulose 2017-10-05 11:22 ` Dave Martin 2017-10-05 11:22 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 11/28] arm64/sve: Core task context handling Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 14:33 ` Catalin Marinas 2017-09-13 14:33 ` Catalin Marinas 2017-09-14 19:55 ` Dave Martin 2017-09-14 19:55 ` Dave Martin 2017-09-20 13:58 ` Catalin Marinas 2017-09-20 13:58 ` Catalin Marinas 2017-10-03 11:11 ` Dave Martin 2017-10-03 11:11 ` Dave Martin 2017-10-04 17:29 ` Catalin Marinas 2017-10-04 17:29 ` Catalin Marinas 2017-10-03 11:33 ` Dave Martin 2017-10-03 11:33 ` Dave Martin 2017-10-05 11:28 ` Catalin Marinas 2017-10-05 11:28 ` Catalin Marinas 2017-10-06 13:10 ` Dave Martin 2017-10-06 13:10 ` Dave Martin 2017-10-06 13:36 ` Catalin Marinas 2017-10-06 13:36 ` Catalin Marinas 2017-10-06 15:15 ` Dave Martin 2017-10-06 15:15 ` Dave Martin 2017-10-06 15:33 ` Catalin Marinas 2017-10-06 15:33 ` Catalin Marinas 2017-09-13 17:26 ` Catalin Marinas 2017-09-13 17:26 ` Catalin Marinas 2017-09-13 19:17 ` Dave Martin 2017-09-13 19:17 ` Dave Martin 2017-09-13 22:21 ` Catalin Marinas 2017-09-13 22:21 ` Catalin Marinas 2017-09-14 19:40 ` Dave Martin 2017-09-14 19:40 ` Dave Martin 2017-09-19 17:13 ` Catalin Marinas 2017-09-19 17:13 ` Catalin Marinas 2017-08-31 17:00 ` [PATCH v2 12/28] arm64/sve: Support vector length resetting for new processes Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 8:47 ` Alex Bennée 2017-09-14 8:47 ` Alex Bennée 2017-09-14 8:47 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 13/28] arm64/sve: Signal handling support Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 9:30 ` Alex Bennée 2017-09-14 9:30 ` Alex Bennée 2017-09-14 9:30 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 14/28] arm64/sve: Backend logic for setting the vector length Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-13 17:29 ` Catalin Marinas 2017-09-13 17:29 ` Catalin Marinas 2017-09-13 19:06 ` Dave Martin 2017-09-13 19:06 ` Dave Martin 2017-09-13 22:11 ` Catalin Marinas 2017-09-13 22:11 ` Catalin Marinas 2017-10-05 16:42 ` Dave Martin 2017-10-05 16:42 ` Dave Martin 2017-10-05 16:53 ` Catalin Marinas 2017-10-05 16:53 ` Catalin Marinas 2017-10-05 17:04 ` Dave Martin 2017-10-05 17:04 ` Dave Martin 2017-09-20 10:57 ` Alan Hayward 2017-09-20 10:57 ` Alan Hayward 2017-09-20 10:59 ` Alan Hayward 2017-09-20 10:59 ` Alan Hayward 2017-09-20 11:09 ` Dave Martin 2017-09-20 11:09 ` Dave Martin 2017-09-20 18:08 ` Alan Hayward 2017-09-20 18:08 ` Alan Hayward 2017-09-21 11:19 ` Dave Martin 2017-09-21 11:19 ` Dave Martin 2017-09-21 11:57 ` Alan Hayward 2017-09-21 11:57 ` Alan Hayward 2017-08-31 17:00 ` [PATCH v2 15/28] arm64: cpufeature: Move sys_caps_initialised declarations Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 9:33 ` Alex Bennée 2017-09-14 9:33 ` Alex Bennée 2017-09-14 9:33 ` Alex Bennée 2017-09-14 9:35 ` Suzuki K Poulose 2017-09-14 9:35 ` Suzuki K Poulose 2017-08-31 17:00 ` [PATCH v2 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 9:45 ` Alex Bennée 2017-09-14 9:45 ` Alex Bennée 2017-09-14 9:45 ` Alex Bennée 2017-09-28 14:22 ` Dave Martin [this message] 2017-09-28 14:22 ` Dave Martin 2017-09-28 17:32 ` Alex Bennée 2017-09-28 17:32 ` Alex Bennée 2017-09-28 17:32 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 17/28] arm64/sve: Preserve SVE registers around kernel-mode NEON use Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 10:52 ` Alex Bennée 2017-09-14 10:52 ` Alex Bennée 2017-09-14 10:52 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 18/28] arm64/sve: Preserve SVE registers around EFI runtime service calls Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 11:01 ` Alex Bennée 2017-09-14 11:01 ` Alex Bennée 2017-09-14 11:01 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-06 16:21 ` Okamoto, Takayuki 2017-09-06 16:21 ` Okamoto, Takayuki 2017-09-06 18:16 ` Dave Martin 2017-09-06 18:16 ` Dave Martin 2017-09-07 5:11 ` Okamoto, Takayuki 2017-09-07 5:11 ` Okamoto, Takayuki 2017-09-07 5:11 ` Okamoto, Takayuki 2017-09-08 13:11 ` Dave Martin 2017-09-08 13:11 ` Dave Martin 2017-09-14 12:57 ` Alex Bennée 2017-09-14 12:57 ` Alex Bennée 2017-09-14 12:57 ` Alex Bennée 2017-09-28 14:57 ` Dave Martin 2017-09-28 14:57 ` Dave Martin 2017-09-29 12:46 ` Dave Martin 2017-09-29 12:46 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 20/28] arm64/sve: Add prctl controls for userspace vector length management Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 13:02 ` Alex Bennée 2017-09-14 13:02 ` Alex Bennée 2017-09-14 13:02 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 21/28] arm64/sve: Add sysctl to set the default vector length for new processes Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 13:05 ` Alex Bennée 2017-09-14 13:05 ` Alex Bennée 2017-09-14 13:05 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 22/28] arm64/sve: KVM: Prevent guests from using SVE Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 13:28 ` Alex Bennée 2017-09-14 13:28 ` Alex Bennée 2017-09-14 13:28 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 13:30 ` Alex Bennée 2017-09-14 13:30 ` Alex Bennée 2017-09-14 13:30 ` Alex Bennée 2017-09-14 13:31 ` Alex Bennée 2017-09-14 13:31 ` Alex Bennée 2017-09-14 13:31 ` Alex Bennée 2017-09-29 13:00 ` Dave Martin 2017-09-29 13:00 ` Dave Martin 2017-09-29 14:43 ` Alex Bennée 2017-09-29 14:43 ` Alex Bennée 2017-09-29 14:43 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-09-14 13:32 ` Alex Bennée 2017-09-14 13:32 ` Alex Bennée 2017-09-14 13:32 ` Alex Bennée 2017-08-31 17:00 ` [PATCH v2 25/28] arm64/sve: Detect SVE and activate runtime support Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` [PATCH v2 26/28] arm64/sve: Add documentation Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-10-05 16:39 ` Szabolcs Nagy 2017-10-05 16:39 ` Szabolcs Nagy 2017-10-05 17:02 ` Dave Martin 2017-10-05 17:02 ` Dave Martin 2017-10-06 15:43 ` Szabolcs Nagy 2017-10-06 15:43 ` Szabolcs Nagy 2017-10-06 17:37 ` Dave Martin 2017-10-06 17:37 ` Dave Martin 2017-10-09 9:34 ` Alex Bennée 2017-10-09 9:34 ` Alex Bennée 2017-10-09 9:34 ` Alex Bennée 2017-10-09 9:49 ` Dave Martin 2017-10-09 9:49 ` Dave Martin 2017-10-09 14:07 ` Alex Bennée 2017-10-09 14:07 ` Alex Bennée 2017-10-09 14:07 ` Alex Bennée 2017-10-09 16:20 ` Dave Martin 2017-10-09 16:20 ` Dave Martin 2017-08-31 17:00 ` [RFC PATCH v2 27/28] arm64: signal: Report signal frame size to userspace via auxv Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:00 ` Dave Martin 2017-08-31 17:01 ` [RFC PATCH v2 28/28] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ Dave Martin 2017-08-31 17:01 ` Dave Martin
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