From: Jagan Teki <jagan@amarulasolutions.com> To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, Icenowy Zheng <icenowy@aosc.io>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width Date: Thu, 1 Nov 2018 00:06:28 +0530 [thread overview] Message-ID: <20181031183634.29640-1-jagan@amarulasolutions.com> (raw) MUX bits for MMC clock register range are 25:24 where 24 is shift and 2 is width So fix the width number from 3 to 2. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2193e1495086..e2bc612f1d3e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -411,7 +411,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -419,7 +419,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -427,7 +427,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); -- 2.18.0.321.gffc6fa0e3
WARNING: multiple messages have this Message-ID (diff)
From: jagan@amarulasolutions.com (Jagan Teki) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width Date: Thu, 1 Nov 2018 00:06:28 +0530 [thread overview] Message-ID: <20181031183634.29640-1-jagan@amarulasolutions.com> (raw) MUX bits for MMC clock register range are 25:24 where 24 is shift and 2 is width So fix the width number from 3 to 2. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2193e1495086..e2bc612f1d3e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -411,7 +411,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -419,7 +419,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -427,7 +427,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); -- 2.18.0.321.gffc6fa0e3
next reply other threads:[~2018-10-31 18:36 UTC|newest] Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-31 18:36 Jagan Teki [this message] 2018-10-31 18:36 ` [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width Jagan Teki 2018-10-31 18:36 ` [PATCH 2/7] arm64: allwinner: h6: Add common orangepi nodes into dtsi Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-11-01 2:53 ` Chen-Yu Tsai 2018-11-01 2:53 ` Chen-Yu Tsai 2018-11-01 2:53 ` Chen-Yu Tsai 2018-11-01 7:13 ` Jagan Teki 2018-11-01 7:13 ` Jagan Teki 2018-11-01 7:13 ` Jagan Teki 2018-11-01 7:20 ` Chen-Yu Tsai 2018-11-01 7:20 ` Chen-Yu Tsai 2018-11-01 7:20 ` Chen-Yu Tsai 2018-10-31 18:36 ` [PATCH 3/7] arm64: allwinner: h6: Add OrangePi Lite2 initial support Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` [PATCH 4/7] arm64: allwinner: h6: Add MMC1 pinmux Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` [PATCH 5/7] arm64: allwinner: h6: Add RTC node Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-11-01 2:55 ` Chen-Yu Tsai 2018-11-01 2:55 ` Chen-Yu Tsai 2018-11-01 2:55 ` Chen-Yu Tsai 2018-11-01 7:33 ` Jagan Teki 2018-11-01 7:33 ` Jagan Teki 2018-11-01 7:33 ` Jagan Teki 2018-11-01 7:53 ` Chen-Yu Tsai 2018-11-01 7:53 ` Chen-Yu Tsai 2018-11-01 7:53 ` Chen-Yu Tsai 2018-11-01 9:02 ` Jagan Teki 2018-11-01 9:02 ` Jagan Teki 2018-11-01 9:02 ` Jagan Teki 2018-11-01 9:35 ` Chen-Yu Tsai 2018-11-01 9:35 ` Chen-Yu Tsai 2018-11-01 9:35 ` Chen-Yu Tsai 2018-10-31 18:36 ` [PATCH 6/7] arm64: allwinner: h6: Add RTC clock to phandle 32kHz external oscillator Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-11-01 2:57 ` Chen-Yu Tsai 2018-11-01 2:57 ` Chen-Yu Tsai 2018-11-01 2:57 ` Chen-Yu Tsai 2018-10-31 18:36 ` [RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support Jagan Teki 2018-10-31 18:36 ` Jagan Teki 2018-11-01 7:35 ` Jagan Teki 2018-11-01 7:35 ` Jagan Teki 2018-11-01 7:35 ` Jagan Teki 2018-11-01 7:58 ` Chen-Yu Tsai 2018-11-01 7:58 ` Chen-Yu Tsai 2018-11-01 7:58 ` Chen-Yu Tsai 2018-11-01 9:08 ` Jagan Teki 2018-11-01 9:08 ` Jagan Teki 2018-11-01 9:08 ` Jagan Teki 2018-11-01 9:49 ` Chen-Yu Tsai 2018-11-01 9:49 ` Chen-Yu Tsai 2018-11-01 9:49 ` Chen-Yu Tsai 2018-11-05 8:41 ` [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width Maxime Ripard 2018-11-05 8:41 ` Maxime Ripard
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