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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.SPARSE: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3)
Date: Thu, 29 Nov 2018 19:56:53 -0000	[thread overview]
Message-ID: <20181129195653.5826.36659@emeril.freedesktop.org> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3)
URL   : https://patchwork.freedesktop.org/series/53184/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Compute DSC pipe config in atomic check
+drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)

Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled
Okay!

Commit: drm/i915/dsc: Define & Compute VESA DSC params
+drivers/gpu/drm/i915/intel_vdsc.c:352:17: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/dsc: Compute Rate Control parameters for DSC
Okay!

Commit: drm/i915/dp: Enable/Disable DSC in DP Sink
Okay!

Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Okay!

Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Okay!

Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
Okay!

Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable
Okay!

Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void)

Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC
Okay!

Commit: i915/dp/fec: Add fec_enable to the crtc state.
Okay!

Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Okay!

Commit: i915/dp/fec: Configure the Forward Error Correction bits.
Okay!

Commit: drm/i915/fec: Disable FEC state.
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  parent reply	other threads:[~2018-11-29 19:56 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28 20:26 [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-28 20:26 ` [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-28 21:36   ` [PATCH v14 " Manasi Navare
2018-11-28 20:26 ` [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-28 20:26 ` [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-29 19:38   ` [CI v15 " Manasi Navare
2018-11-28 20:26 ` [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-28 20:26 ` [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-28 20:26 ` [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-28 20:26 ` [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-28 20:26 ` [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-28 20:26 ` [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-28 20:26 ` [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-28 20:26 ` [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-28 20:26 ` [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-28 20:26 ` [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-28 20:26 ` [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-28 20:26 ` [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-28 20:26 ` [CI v13 17/17] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-28 21:01 ` ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Patchwork
2018-11-28 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) Patchwork
2018-11-28 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-28 23:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 10:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-29 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
2018-11-29 19:56 ` Patchwork [this message]
2018-11-29 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 20:52 ` [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-30 12:52 ` ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork

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