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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Date: Thu, 29 Nov 2018 12:52:44 -0800	[thread overview]
Message-ID: <20181129205243.GC32458@intel.com> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>

Pushed to dinq, thanks for the patch and the review.

Manasi

On Wed, Nov 28, 2018 at 12:26:12PM -0800, Manasi Navare wrote:
> Basic DSC parameters and DSC configuration data needs to be computed
> for each of the requested mode during atomic check. This is
> required since for certain modes, valid DSC parameters and config
> data might not be computed in which case compression cannot be
> enabled for that mode.
> For that reason we need to add these params and config structure
> to the intel_crtc_state so that if valid this state information
> can directly be used while enabling DSC in atomic commit.
> 
> v2:
> * Rebase on drm-tip (Manasi)
> 
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 1 +
>  drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f763b30f98d9..183aae996305 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -53,6 +53,7 @@
>  #include <drm/drm_auth.h>
>  #include <drm/drm_cache.h>
>  #include <drm/drm_util.h>
> +#include <drm/drm_dsc.h>
>  
>  #include "i915_fixed.h"
>  #include "i915_params.h"
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a62d77b76291..270212fa43a0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -937,6 +937,15 @@ struct intel_crtc_state {
>  
>  	/* Output down scaling is done in LSPCON device */
>  	bool lspcon_downsampling;
> +
> +	/* Display Stream compression state */
> +	struct {
> +		bool compression_enable;
> +		bool dsc_split;
> +		u16 compressed_bpp;
> +		u8 slice_count;
> +	} dsc_params;
> +	struct drm_dsc_config dp_dsc_cfg;
>  };
>  
>  struct intel_crtc {
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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  parent reply	other threads:[~2018-11-29 20:49 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28 20:26 [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-28 20:26 ` [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-28 21:36   ` [PATCH v14 " Manasi Navare
2018-11-28 20:26 ` [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-28 20:26 ` [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-29 19:38   ` [CI v15 " Manasi Navare
2018-11-28 20:26 ` [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-28 20:26 ` [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-28 20:26 ` [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-28 20:26 ` [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-28 20:26 ` [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-28 20:26 ` [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-28 20:26 ` [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-28 20:26 ` [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-28 20:26 ` [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-28 20:26 ` [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-28 20:26 ` [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-28 20:26 ` [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-28 20:26 ` [CI v13 17/17] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-28 21:01 ` ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Patchwork
2018-11-28 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) Patchwork
2018-11-28 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-28 23:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 10:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-29 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
2018-11-29 19:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-29 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 20:52 ` Manasi Navare [this message]
2018-11-30 12:52 ` ✗ Fi.CI.IGT: failure " Patchwork

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