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From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	"Z.q. Hou" <zhiqiang.hou@nxp.com>
Subject: [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader
Date: Mon, 11 Mar 2019 09:32:40 +0000	[thread overview]
Message-ID: <20190311093130.7209-21-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V4:
 - no change

 .../controller/mobiveil/pcie-mobiveil-host.c   |  7 +++++++
 .../pci/controller/mobiveil/pcie-mobiveil.c    | 18 ++++++++++++++++++
 .../pci/controller/mobiveil/pcie-mobiveil.h    |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index d1765d572f44..d028cdf31d0e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
+	int i;
+
+	/* Disable all inbound/outbound windows */
+	for (i = 0; i < pcie->apio_wins; i++)
+		mobiveil_pcie_disable_ob_win(pcie, i);
+	for (i = 0; i < pcie->ppio_wins; i++)
+		mobiveil_pcie_disable_ib_win(pcie, i);
 
 	/* setup bus numbers */
 	value = csr_readl(pcie, PCI_PRIMARY_BUS);
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 370658d6546d..49d471b75925 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 
 	return -ETIMEDOUT;
 }
+
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
+	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
+	csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
+}
+
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
+	val &= ~(1 << WIN_ENABLE_SHIFT);
+	csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
+}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index eb4cb61291a8..81685840b378 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
 u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
 void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>
Cc: "M.h. Lian" <minghuan.lian@nxp.com>,
	"Z.q. Hou" <zhiqiang.hou@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	Mingkai Hu <mingkai.hu@nxp.com>
Subject: [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader
Date: Mon, 11 Mar 2019 09:32:40 +0000	[thread overview]
Message-ID: <20190311093130.7209-21-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V4:
 - no change

 .../controller/mobiveil/pcie-mobiveil-host.c   |  7 +++++++
 .../pci/controller/mobiveil/pcie-mobiveil.c    | 18 ++++++++++++++++++
 .../pci/controller/mobiveil/pcie-mobiveil.h    |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index d1765d572f44..d028cdf31d0e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
+	int i;
+
+	/* Disable all inbound/outbound windows */
+	for (i = 0; i < pcie->apio_wins; i++)
+		mobiveil_pcie_disable_ob_win(pcie, i);
+	for (i = 0; i < pcie->ppio_wins; i++)
+		mobiveil_pcie_disable_ib_win(pcie, i);
 
 	/* setup bus numbers */
 	value = csr_readl(pcie, PCI_PRIMARY_BUS);
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 370658d6546d..49d471b75925 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 
 	return -ETIMEDOUT;
 }
+
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
+	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
+	csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
+}
+
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
+{
+	u32 val;
+
+	val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
+	val &= ~(1 << WIN_ENABLE_SHIFT);
+	csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
+}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index eb4cb61291a8..81685840b378 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
 			u64 pci_addr, u32 type, u64 size);
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
 u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
 void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-03-11  9:32 UTC|newest]

Thread overview: 158+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-11  9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11  9:29 ` Z.q. Hou
2019-03-11  9:29 ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 01/28] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 02/28] PCI: mobiveil: format the code without function change Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 03/28] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 04/28] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 05/28] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 06/28] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 07/28] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:30   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 08/28] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 09/28] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11 14:08   ` Bjorn Helgaas
2019-03-11 14:08     ` Bjorn Helgaas
2019-03-11 14:08     ` Bjorn Helgaas
2019-03-12  4:42     ` Z.q. Hou
2019-03-12  4:42       ` Z.q. Hou
2019-03-12  4:42       ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11 14:14   ` Bjorn Helgaas
2019-03-11 14:14     ` Bjorn Helgaas
2019-03-11 14:14     ` Bjorn Helgaas
2019-03-12  9:17     ` Z.q. Hou
2019-03-12  9:17       ` Z.q. Hou
2019-03-12  9:17       ` Z.q. Hou
2019-03-13 10:59       ` Subrahmanya Lingappa
2019-03-13 10:59         ` Subrahmanya Lingappa
2019-03-13 10:59         ` Subrahmanya Lingappa
2019-03-11  9:31 ` [PATCHv4 12/28] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 13/28] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 14/28] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 15/28] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:31   ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 16/28] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-26 17:34   ` Lorenzo Pieralisi
2019-03-26 17:34     ` Lorenzo Pieralisi
2019-03-26 17:34     ` Lorenzo Pieralisi
2019-03-27  2:04     ` Z.q. Hou
2019-03-27  2:04       ` Z.q. Hou
2019-03-27 17:39       ` Lorenzo Pieralisi
2019-03-27 17:39         ` Lorenzo Pieralisi
2019-03-27 17:39         ` Lorenzo Pieralisi
2019-03-28  2:09         ` Z.q. Hou
2019-03-28  2:09           ` Z.q. Hou
2019-03-28 16:09           ` Lorenzo Pieralisi
2019-03-28 16:09             ` Lorenzo Pieralisi
2019-03-28 16:09             ` Lorenzo Pieralisi
2019-03-29  6:07             ` Z.q. Hou
2019-03-29  6:07               ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 17/28] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 18/28] PCI: mobiveil: add link up condition check Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 19/28] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32 ` Z.q. Hou [this message]
2019-03-11  9:32   ` [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:32   ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11 22:11   ` Rob Herring
2019-03-11 22:11     ` Rob Herring
2019-03-11 22:11     ` Rob Herring
2019-03-12  3:17     ` Z.q. Hou
2019-03-12  3:17       ` Z.q. Hou
2019-03-12  3:17       ` Z.q. Hou
2019-03-12  9:42   ` Z.q. Hou
2019-03-12  9:42     ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 24/28] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11 14:01   ` Bjorn Helgaas
2019-03-11 14:01     ` Bjorn Helgaas
2019-03-11 14:01     ` Bjorn Helgaas
2019-03-12  4:40     ` Z.q. Hou
2019-03-12  4:40       ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-13 14:51   ` Z.q. Hou
2019-03-13 14:51     ` Z.q. Hou
2019-03-13 14:51     ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11 17:34   ` Bjorn Helgaas
2019-03-11 17:34     ` Bjorn Helgaas
2019-03-11 17:34     ` Bjorn Helgaas
2019-03-12  9:34     ` Z.q. Hou
2019-03-12  9:34       ` Z.q. Hou
2019-03-12  9:34       ` Z.q. Hou
2019-03-12 13:34       ` Bjorn Helgaas
2019-03-12 13:34         ` Bjorn Helgaas
2019-03-12 13:34         ` Bjorn Helgaas
2019-03-13 14:49         ` Z.q. Hou
2019-03-13 14:49           ` Z.q. Hou
2019-03-13 14:49           ` Z.q. Hou
2019-03-13 14:51   ` Z.q. Hou
2019-03-13 14:51     ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 28/28] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11  9:33   ` Z.q. Hou
2019-03-11 13:33 ` [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Bjorn Helgaas
2019-03-11 13:33   ` Bjorn Helgaas
2019-03-11 13:33   ` Bjorn Helgaas
2019-03-12  4:18   ` Z.q. Hou
2019-03-12  4:18     ` Z.q. Hou
2019-03-26 17:37 ` Lorenzo Pieralisi
2019-03-26 17:37   ` Lorenzo Pieralisi
2019-03-26 17:37   ` Lorenzo Pieralisi
2019-03-27  2:11   ` Z.q. Hou
2019-03-27  2:11     ` Z.q. Hou
2019-03-27  2:11     ` Z.q. Hou

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