From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com> Cc: Mingkai Hu <mingkai.hu@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com> Subject: [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Date: Mon, 11 Mar 2019 09:32:57 +0000 [thread overview] Message-ID: <20190311093130.7209-23-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Make the mobiveil_host_init function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon Hot-reset. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> --- V4: - no change .../controller/mobiveil/pcie-mobiveil-host.c | 41 ++++++++++--------- .../pci/controller/mobiveil/pcie-mobiveil.h | 3 +- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index d028cdf31d0e..e8d0c4989013 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -217,7 +217,7 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } -static int mobiveil_host_init(struct mobiveil_pcie *pcie) +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) { u32 value, pab_ctrl, type; struct resource_entry *win; @@ -229,11 +229,16 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) for (i = 0; i < pcie->ppio_wins; i++) mobiveil_pcie_disable_ib_win(pcie, i); - /* setup bus numbers */ - value = csr_readl(pcie, PCI_PRIMARY_BUS); - value &= 0xff000000; - value |= 0x00ff0100; - csr_writel(pcie, value, PCI_PRIMARY_BUS); + pcie->ib_wins_configured = 0; + pcie->ob_wins_configured = 0; + + if (!reinit) { + /* setup bus numbers */ + value = csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + } /* * program Bus Master Enable Bit in Command Register in PAB Config @@ -279,7 +284,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ - resource_list_for_each_entry(win, &pcie->resources) { + resource_list_for_each_entry(win, pcie->resources) { if (resource_type(win->res) == IORESOURCE_MEM) { type = MEM_WINDOW_TYPE; } else if (resource_type(win->res) == IORESOURCE_IO) { @@ -550,8 +555,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) resource_size_t iobase; int ret; - INIT_LIST_HEAD(&pcie->resources); - ret = mobiveil_pcie_parse_dt(pcie); if (ret) { dev_err(dev, "Parsing DT failed, ret: %x\n", ret); @@ -565,34 +568,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) /* parse the host bridge base addresses from the device tree file */ ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, - &pcie->resources, &iobase); + &bridge->windows, &iobase); if (ret) { dev_err(dev, "Getting bridge resources failed\n"); return ret; } + pcie->resources = &bridge->windows; + /* * configure all inbound and outbound windows and prepare the RC for * config access */ - ret = mobiveil_host_init(pcie); + ret = mobiveil_host_init(pcie, false); if (ret) { dev_err(dev, "Failed to initialize host\n"); - goto error; + return ret; } ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { dev_err(dev, "Interrupt init failed\n"); - goto error; + return ret; } - ret = devm_request_pci_bus_resources(dev, &pcie->resources); + ret = devm_request_pci_bus_resources(dev, pcie->resources); if (ret) - goto error; + return ret; /* Initialize bridge */ - list_splice_init(&pcie->resources, &bridge->windows); bridge->dev.parent = dev; bridge->sysdata = pcie; bridge->busnr = pcie->rp.root_bus_nr; @@ -608,7 +612,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) /* setup the kernel resources for the newly added PCIe root bus */ ret = pci_scan_root_bus_bridge(bridge); if (ret) - goto error; + return ret; bus = bridge->bus; @@ -618,7 +622,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) pci_bus_add_devices(bus); return 0; -error: - pci_free_resource_list(&pcie->resources); - return ret; } diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 933c2f34bc52..0f5303962e88 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -152,7 +152,7 @@ struct mobiveil_pab_ops { struct mobiveil_pcie { struct platform_device *pdev; - struct list_head resources; + struct list_head *resources; void __iomem *csr_axi_slave_base; /* PAB registers base */ phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ void __iomem *apb_csr_base; /* MSI register base */ @@ -165,6 +165,7 @@ struct mobiveil_pcie { }; int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie); void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com> Cc: "M.h. Lian" <minghuan.lian@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com> Subject: [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Date: Mon, 11 Mar 2019 09:32:57 +0000 [thread overview] Message-ID: <20190311093130.7209-23-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Make the mobiveil_host_init function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon Hot-reset. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> --- V4: - no change .../controller/mobiveil/pcie-mobiveil-host.c | 41 ++++++++++--------- .../pci/controller/mobiveil/pcie-mobiveil.h | 3 +- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index d028cdf31d0e..e8d0c4989013 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -217,7 +217,7 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } -static int mobiveil_host_init(struct mobiveil_pcie *pcie) +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) { u32 value, pab_ctrl, type; struct resource_entry *win; @@ -229,11 +229,16 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) for (i = 0; i < pcie->ppio_wins; i++) mobiveil_pcie_disable_ib_win(pcie, i); - /* setup bus numbers */ - value = csr_readl(pcie, PCI_PRIMARY_BUS); - value &= 0xff000000; - value |= 0x00ff0100; - csr_writel(pcie, value, PCI_PRIMARY_BUS); + pcie->ib_wins_configured = 0; + pcie->ob_wins_configured = 0; + + if (!reinit) { + /* setup bus numbers */ + value = csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + } /* * program Bus Master Enable Bit in Command Register in PAB Config @@ -279,7 +284,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ - resource_list_for_each_entry(win, &pcie->resources) { + resource_list_for_each_entry(win, pcie->resources) { if (resource_type(win->res) == IORESOURCE_MEM) { type = MEM_WINDOW_TYPE; } else if (resource_type(win->res) == IORESOURCE_IO) { @@ -550,8 +555,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) resource_size_t iobase; int ret; - INIT_LIST_HEAD(&pcie->resources); - ret = mobiveil_pcie_parse_dt(pcie); if (ret) { dev_err(dev, "Parsing DT failed, ret: %x\n", ret); @@ -565,34 +568,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) /* parse the host bridge base addresses from the device tree file */ ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, - &pcie->resources, &iobase); + &bridge->windows, &iobase); if (ret) { dev_err(dev, "Getting bridge resources failed\n"); return ret; } + pcie->resources = &bridge->windows; + /* * configure all inbound and outbound windows and prepare the RC for * config access */ - ret = mobiveil_host_init(pcie); + ret = mobiveil_host_init(pcie, false); if (ret) { dev_err(dev, "Failed to initialize host\n"); - goto error; + return ret; } ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { dev_err(dev, "Interrupt init failed\n"); - goto error; + return ret; } - ret = devm_request_pci_bus_resources(dev, &pcie->resources); + ret = devm_request_pci_bus_resources(dev, pcie->resources); if (ret) - goto error; + return ret; /* Initialize bridge */ - list_splice_init(&pcie->resources, &bridge->windows); bridge->dev.parent = dev; bridge->sysdata = pcie; bridge->busnr = pcie->rp.root_bus_nr; @@ -608,7 +612,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) /* setup the kernel resources for the newly added PCIe root bus */ ret = pci_scan_root_bus_bridge(bridge); if (ret) - goto error; + return ret; bus = bridge->bus; @@ -618,7 +622,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) pci_bus_add_devices(bus); return 0; -error: - pci_free_resource_list(&pcie->resources); - return ret; } diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 933c2f34bc52..0f5303962e88 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -152,7 +152,7 @@ struct mobiveil_pab_ops { struct mobiveil_pcie { struct platform_device *pdev; - struct list_head resources; + struct list_head *resources; void __iomem *csr_axi_slave_base; /* PAB registers base */ phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ void __iomem *apb_csr_base; /* MSI register base */ @@ -165,6 +165,7 @@ struct mobiveil_pcie { }; int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie); void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-03-11 9:33 UTC|newest] Thread overview: 158+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-11 9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou 2019-03-11 9:29 ` Z.q. Hou 2019-03-11 9:29 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 01/28] PCI: mobiveil: uniform the register accessors Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 02/28] PCI: mobiveil: format the code without function change Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 03/28] PCI: mobiveil: correct the returned error number Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 04/28] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 05/28] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 06/28] PCI: mobiveil: replace the resource list iteration function Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 07/28] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 08/28] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 09/28] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-12 4:42 ` Z.q. Hou 2019-03-12 4:42 ` Z.q. Hou 2019-03-12 4:42 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-12 9:17 ` Z.q. Hou 2019-03-12 9:17 ` Z.q. Hou 2019-03-12 9:17 ` Z.q. Hou 2019-03-13 10:59 ` Subrahmanya Lingappa 2019-03-13 10:59 ` Subrahmanya Lingappa 2019-03-13 10:59 ` Subrahmanya Lingappa 2019-03-11 9:31 ` [PATCHv4 12/28] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 13/28] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 14/28] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 15/28] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 16/28] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-27 2:04 ` Z.q. Hou 2019-03-27 2:04 ` Z.q. Hou 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-28 2:09 ` Z.q. Hou 2019-03-28 2:09 ` Z.q. Hou 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-29 6:07 ` Z.q. Hou 2019-03-29 6:07 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 17/28] PCI: mobiveil: fix the checking of valid device Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 18/28] PCI: mobiveil: add link up condition check Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 19/28] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou [this message] 2019-03-11 9:32 ` [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 22:11 ` Rob Herring 2019-03-11 22:11 ` Rob Herring 2019-03-11 22:11 ` Rob Herring 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 9:42 ` Z.q. Hou 2019-03-12 9:42 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 24/28] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-12 4:40 ` Z.q. Hou 2019-03-12 4:40 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 28/28] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 13:33 ` [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Bjorn Helgaas 2019-03-11 13:33 ` Bjorn Helgaas 2019-03-11 13:33 ` Bjorn Helgaas 2019-03-12 4:18 ` Z.q. Hou 2019-03-12 4:18 ` Z.q. Hou 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-27 2:11 ` Z.q. Hou 2019-03-27 2:11 ` Z.q. Hou 2019-03-27 2:11 ` Z.q. Hou
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