From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Subject: [PATCH i-g-t 16/24] drm-uapi: Import i915_drm.h upto 364df3d04d51 Date: Fri, 22 Mar 2019 09:21:47 +0000 [thread overview] Message-ID: <20190322092155.1656-16-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20190322092155.1656-1-chris@chris-wilson.co.uk> commit 364df3d04d51f0aad13b898f3dffca8c2d03d2b3 (HEAD) Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Jun 30 13:40:53 2017 +0100 drm/i915: Allow specification of parallel execbuf Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- include/drm-uapi/i915_drm.h | 137 +++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 2 deletions(-) diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 353127daa..cb6d66178 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -126,6 +126,9 @@ enum drm_i915_gem_engine_class { I915_ENGINE_CLASS_INVALID = -1 }; +#define I915_ENGINE_CLASS_INVALID_NONE -1 +#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0 + /** * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 * @@ -590,6 +593,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_MMAP_GTT_COHERENT 52 +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel + * execution through use of explicit fence support. + * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. + */ +#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { @@ -1112,7 +1121,16 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_FENCE_ARRAY (1<<19) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) +/* + * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent + * a sync_file fd to wait upon (in a nonblocking manner) prior to executing + * the batch. + * + * Returns -EINVAL if the sync_file fd cannot be found. + */ +#define I915_EXEC_FENCE_SUBMIT (1 << 20) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ @@ -1511,6 +1529,30 @@ struct drm_i915_gem_context_param { * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. */ #define I915_CONTEXT_PARAM_VM 0x9 + +/* + * I915_CONTEXT_PARAM_ENGINES: + * + * Bind this context to operate on this subset of available engines. Henceforth, + * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as + * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] + * and upwards. Slots 0...N are filled in using the specified (class, instance). + * Use + * engine_class: I915_ENGINE_CLASS_INVALID, + * engine_instance: I915_ENGINE_CLASS_INVALID_NONE + * to specify a gap in the array that can be filled in later, e.g. by a + * virtual engine used for load balancing. + * + * Setting the number of engines bound to the context to 0, by passing a zero + * sized argument, will revert back to default settings. + * + * See struct i915_context_param_engines. + * + * Extensions: + * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) + * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) + */ +#define I915_CONTEXT_PARAM_ENGINES 0xa /* Must be kept compact -- no holes and well documented */ __u64 value; @@ -1545,9 +1587,10 @@ struct drm_i915_gem_context_param_sseu { __u16 engine_instance; /* - * Unused for now. Must be cleared to zero. + * Unknown flags must be cleared to zero. */ __u32 flags; +#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) /* * Mask of slices to enable for the context. Valid values are a subset @@ -1575,12 +1618,102 @@ struct drm_i915_gem_context_param_sseu { __u32 rsvd; }; +/* + * i915_context_engines_load_balance: + * + * Enable load balancing across this set of engines. + * + * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when + * used will proxy the execbuffer request onto one of the set of engines + * in such a way as to distribute the load evenly across the set. + * + * The set of engines must be compatible (e.g. the same HW class) as they + * will share the same logical GPU context and ring. + * + * To intermix rendering with the virtual engine and direct rendering onto + * the backing engines (bypassing the load balancing proxy), the context must + * be defined to use a single timeline for all engines. + */ +struct i915_context_engines_load_balance { + struct i915_user_extension base; + + __u16 engine_index; + __u16 mbz16; /* reserved for future use; must be zero */ + __u32 flags; /* all undefined flags must be zero */ + + __u64 engines_mask; /* selection mask of engines[] */ + + __u64 mbz64[4]; /* reserved for future use; must be zero */ +}; + +/* + * i915_context_engines_bond: + * + * Constructed bonded pairs for execution within a virtual engine. + * + * All engines are equal, but some are more equal than others. Given + * the distribution of resources in the HW, it may be preferable to run + * a request on a given subset of engines in parallel to a request on a + * specific engine. We enable this selection of engines within a virtual + * engine by specifying bonding pairs, for any given master engine we will + * only execute on one of the corresponding siblings within the virtual engine. + * + * To execute a request in parallel on the master engine and a sibling requires + * coordination with a I915_EXEC_FENCE_SUBMIT. + */ +struct i915_context_engines_bond { + struct i915_user_extension base; + + __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ + __u16 mbz; + + __u16 master_class; + __u16 master_instance; + + __u64 sibling_mask; /* bitmask of BIT(sibling_index) wrt the v.engine */ + __u64 flags; /* all undefined flags must be zero */ +}; + +struct i915_context_param_engines { + __u64 extensions; /* linked chain of extension blocks, 0 terminates */ +#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 +#define I915_CONTEXT_ENGINES_EXT_BOND 1 + + struct { + __u16 engine_class; /* see enum drm_i915_gem_engine_class */ + __u16 engine_instance; + } class_instance[0]; +} __attribute__((packed)); + +#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ + __u64 extensions; \ + struct { \ + __u16 engine_class; \ + __u16 engine_instance; \ + } class_instance[N__]; \ +} __attribute__((packed)) name__ + struct drm_i915_gem_context_create_ext_setparam { #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 struct i915_user_extension base; struct drm_i915_gem_context_param param; }; +struct drm_i915_gem_context_create_ext_clone { +#define I915_CONTEXT_CREATE_EXT_CLONE 1 + struct i915_user_extension base; + __u32 clone_id; + __u32 flags; +#define I915_CONTEXT_CLONE_FLAGS (1u << 0) +#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 1) +#define I915_CONTEXT_CLONE_SSEU (1u << 2) +#define I915_CONTEXT_CLONE_TIMELINE (1u << 3) +#define I915_CONTEXT_CLONE_VM (1u << 4) +#define I915_CONTEXT_CLONE_ENGINES (1u << 5) +#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1) + __u64 rsvd; +}; + struct drm_i915_gem_context_destroy { __u32 ctx_id; __u32 pad; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Subject: [igt-dev] [PATCH i-g-t 16/24] drm-uapi: Import i915_drm.h upto 364df3d04d51 Date: Fri, 22 Mar 2019 09:21:47 +0000 [thread overview] Message-ID: <20190322092155.1656-16-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20190322092155.1656-1-chris@chris-wilson.co.uk> commit 364df3d04d51f0aad13b898f3dffca8c2d03d2b3 (HEAD) Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Jun 30 13:40:53 2017 +0100 drm/i915: Allow specification of parallel execbuf Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- include/drm-uapi/i915_drm.h | 137 +++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 2 deletions(-) diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 353127daa..cb6d66178 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -126,6 +126,9 @@ enum drm_i915_gem_engine_class { I915_ENGINE_CLASS_INVALID = -1 }; +#define I915_ENGINE_CLASS_INVALID_NONE -1 +#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0 + /** * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 * @@ -590,6 +593,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_MMAP_GTT_COHERENT 52 +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel + * execution through use of explicit fence support. + * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. + */ +#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { @@ -1112,7 +1121,16 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_FENCE_ARRAY (1<<19) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) +/* + * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent + * a sync_file fd to wait upon (in a nonblocking manner) prior to executing + * the batch. + * + * Returns -EINVAL if the sync_file fd cannot be found. + */ +#define I915_EXEC_FENCE_SUBMIT (1 << 20) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ @@ -1511,6 +1529,30 @@ struct drm_i915_gem_context_param { * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. */ #define I915_CONTEXT_PARAM_VM 0x9 + +/* + * I915_CONTEXT_PARAM_ENGINES: + * + * Bind this context to operate on this subset of available engines. Henceforth, + * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as + * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] + * and upwards. Slots 0...N are filled in using the specified (class, instance). + * Use + * engine_class: I915_ENGINE_CLASS_INVALID, + * engine_instance: I915_ENGINE_CLASS_INVALID_NONE + * to specify a gap in the array that can be filled in later, e.g. by a + * virtual engine used for load balancing. + * + * Setting the number of engines bound to the context to 0, by passing a zero + * sized argument, will revert back to default settings. + * + * See struct i915_context_param_engines. + * + * Extensions: + * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) + * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) + */ +#define I915_CONTEXT_PARAM_ENGINES 0xa /* Must be kept compact -- no holes and well documented */ __u64 value; @@ -1545,9 +1587,10 @@ struct drm_i915_gem_context_param_sseu { __u16 engine_instance; /* - * Unused for now. Must be cleared to zero. + * Unknown flags must be cleared to zero. */ __u32 flags; +#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) /* * Mask of slices to enable for the context. Valid values are a subset @@ -1575,12 +1618,102 @@ struct drm_i915_gem_context_param_sseu { __u32 rsvd; }; +/* + * i915_context_engines_load_balance: + * + * Enable load balancing across this set of engines. + * + * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when + * used will proxy the execbuffer request onto one of the set of engines + * in such a way as to distribute the load evenly across the set. + * + * The set of engines must be compatible (e.g. the same HW class) as they + * will share the same logical GPU context and ring. + * + * To intermix rendering with the virtual engine and direct rendering onto + * the backing engines (bypassing the load balancing proxy), the context must + * be defined to use a single timeline for all engines. + */ +struct i915_context_engines_load_balance { + struct i915_user_extension base; + + __u16 engine_index; + __u16 mbz16; /* reserved for future use; must be zero */ + __u32 flags; /* all undefined flags must be zero */ + + __u64 engines_mask; /* selection mask of engines[] */ + + __u64 mbz64[4]; /* reserved for future use; must be zero */ +}; + +/* + * i915_context_engines_bond: + * + * Constructed bonded pairs for execution within a virtual engine. + * + * All engines are equal, but some are more equal than others. Given + * the distribution of resources in the HW, it may be preferable to run + * a request on a given subset of engines in parallel to a request on a + * specific engine. We enable this selection of engines within a virtual + * engine by specifying bonding pairs, for any given master engine we will + * only execute on one of the corresponding siblings within the virtual engine. + * + * To execute a request in parallel on the master engine and a sibling requires + * coordination with a I915_EXEC_FENCE_SUBMIT. + */ +struct i915_context_engines_bond { + struct i915_user_extension base; + + __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ + __u16 mbz; + + __u16 master_class; + __u16 master_instance; + + __u64 sibling_mask; /* bitmask of BIT(sibling_index) wrt the v.engine */ + __u64 flags; /* all undefined flags must be zero */ +}; + +struct i915_context_param_engines { + __u64 extensions; /* linked chain of extension blocks, 0 terminates */ +#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 +#define I915_CONTEXT_ENGINES_EXT_BOND 1 + + struct { + __u16 engine_class; /* see enum drm_i915_gem_engine_class */ + __u16 engine_instance; + } class_instance[0]; +} __attribute__((packed)); + +#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ + __u64 extensions; \ + struct { \ + __u16 engine_class; \ + __u16 engine_instance; \ + } class_instance[N__]; \ +} __attribute__((packed)) name__ + struct drm_i915_gem_context_create_ext_setparam { #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 struct i915_user_extension base; struct drm_i915_gem_context_param param; }; +struct drm_i915_gem_context_create_ext_clone { +#define I915_CONTEXT_CREATE_EXT_CLONE 1 + struct i915_user_extension base; + __u32 clone_id; + __u32 flags; +#define I915_CONTEXT_CLONE_FLAGS (1u << 0) +#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 1) +#define I915_CONTEXT_CLONE_SSEU (1u << 2) +#define I915_CONTEXT_CLONE_TIMELINE (1u << 3) +#define I915_CONTEXT_CLONE_VM (1u << 4) +#define I915_CONTEXT_CLONE_ENGINES (1u << 5) +#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1) + __u64 rsvd; +}; + struct drm_i915_gem_context_destroy { __u32 ctx_id; __u32 pad; -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev
next prev parent reply other threads:[~2019-03-22 9:21 UTC|newest] Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-22 9:21 [PATCH i-g-t 01/24] i915/gem_exec_latency: Measure the latency of context switching Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 02/24] lib: Add GPU power measurement Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 8:36 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 8:36 ` Tvrtko Ursulin 2019-03-26 8:49 ` Chris Wilson 2019-03-26 8:49 ` Chris Wilson 2019-03-26 9:18 ` [PATCH i-g-t v2] " Chris Wilson 2019-03-26 9:18 ` [igt-dev] " Chris Wilson 2019-03-26 9:52 ` Tvrtko Ursulin 2019-03-26 9:52 ` Tvrtko Ursulin 2019-03-26 10:06 ` Chris Wilson 2019-03-26 10:06 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 03/24] i915/gem_exec_schedule: Measure semaphore power consumption Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 8:46 ` Tvrtko Ursulin 2019-03-26 8:46 ` [Intel-gfx] " Tvrtko Ursulin 2019-03-26 9:23 ` Chris Wilson 2019-03-26 9:23 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 04/24] i915/gem_exec_whisper: Measure total power consumed Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 8:47 ` Tvrtko Ursulin 2019-03-26 8:47 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 05/24] i915/gem_exec_schedule: Verify that using HW semaphores doesn't block Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 9:19 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 9:19 ` Tvrtko Ursulin 2019-03-26 10:03 ` Chris Wilson 2019-03-26 10:03 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 06/24] i915/gem_exec_nop: poll-sequential requires ordering between rings Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 9:38 ` Tvrtko Ursulin 2019-03-26 9:38 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 07/24] i915/gem_sync: Make switch-default asymmetric Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 9:57 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 9:57 ` [Intel-gfx] " Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 08/24] i915/gem_ctx_param: Remove kneecapping Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 9:58 ` Tvrtko Ursulin 2019-03-26 9:58 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 09/24] i915/gem_exec_big: Add a single shot test Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 10:06 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 10:06 ` Tvrtko Ursulin 2019-03-26 10:21 ` Chris Wilson 2019-03-26 10:21 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 10/24] kms_fence_pin_leak: Ask for the GPU before use Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:10 ` Tvrtko Ursulin 2019-03-26 10:10 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 11/24] drm-uapi: Import i915_drm.h upto 53073249452d Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 12/24] lib/i915: Improve gem_context error messages Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:14 ` Tvrtko Ursulin 2019-03-26 10:14 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 13/24] i915/gem_ctx_param: Test set/get (copy) VM Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:22 ` Tvrtko Ursulin 2019-03-26 10:22 ` Tvrtko Ursulin 2019-03-26 10:33 ` Tvrtko Ursulin 2019-03-26 10:33 ` Tvrtko Ursulin 2019-03-26 10:51 ` Chris Wilson 2019-03-26 10:51 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 14/24] i915/gem_ctx_create: Basic checks for constructor properties Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:46 ` Tvrtko Ursulin 2019-03-26 10:46 ` Tvrtko Ursulin 2019-03-26 11:06 ` Chris Wilson 2019-03-26 11:06 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 15/24] i915: Add gem_vm_create Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 11:21 ` Tvrtko Ursulin 2019-03-26 11:21 ` Tvrtko Ursulin 2019-03-26 11:37 ` Chris Wilson 2019-03-26 11:37 ` Chris Wilson 2019-03-26 11:48 ` Tvrtko Ursulin 2019-03-26 11:48 ` Tvrtko Ursulin 2019-03-26 14:11 ` Chris Wilson 2019-03-26 14:11 ` Chris Wilson 2019-03-22 9:21 ` Chris Wilson [this message] 2019-03-22 9:21 ` [igt-dev] [PATCH i-g-t 16/24] drm-uapi: Import i915_drm.h upto 364df3d04d51 Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 17/24] i915: Add gem_ctx_clone Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 15:44 ` Tvrtko Ursulin 2019-03-26 15:44 ` Tvrtko Ursulin 2019-03-26 15:49 ` Chris Wilson 2019-03-26 15:49 ` Chris Wilson 2019-03-26 15:54 ` Chris Wilson 2019-03-26 15:54 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 18/24] i915: Exercise creating context with shared GTT Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 19/24] i915/gem_ctx_switch: Exercise queues Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 20/24] i915/gem_exec_whisper: Fork all-engine tests one-per-engine Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 21/24] i915/gem_exec_whisper: debugfs/next_seqno is defunct Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 22/24] i915: Add gem_ctx_engines Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 16:40 ` Andi Shyti 2019-03-22 16:40 ` [igt-dev] " Andi Shyti 2019-03-22 16:48 ` Chris Wilson 2019-03-22 16:48 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 23/24] i915: Add gem_exec_balancer Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 24/24] i915/gem_exec_balancer: Exercise bonded pairs Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 10:22 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/24] i915/gem_exec_latency: Measure the latency of context switching Patchwork 2019-03-23 6:38 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2019-03-26 11:00 ` [igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,01/24] i915/gem_exec_latency: Measure the latency of context switching (rev2) Patchwork
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