From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Subject: [PATCH i-g-t 06/24] i915/gem_exec_nop: poll-sequential requires ordering between rings Date: Fri, 22 Mar 2019 09:21:37 +0000 [thread overview] Message-ID: <20190322092155.1656-6-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20190322092155.1656-1-chris@chris-wilson.co.uk> In order to correctly serialise the order of execution between rings, we need to flag the scratch address as being written. Make it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- tests/i915/gem_exec_nop.c | 152 +++++++++++++++++++++++++++++++++----- 1 file changed, 133 insertions(+), 19 deletions(-) diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c index 59a08ad08..b91b4d0f6 100644 --- a/tests/i915/gem_exec_nop.c +++ b/tests/i915/gem_exec_nop.c @@ -104,7 +104,7 @@ static double nop_on_ring(int fd, uint32_t handle, unsigned ring_id, return elapsed(&start, &now); } -static void poll_ring(int fd, unsigned ring, const char *name, int timeout) +static void poll_ring(int fd, unsigned engine, const char *name, int timeout) { const int gen = intel_gen(intel_get_drm_devid(fd)); const uint32_t MI_ARB_CHK = 0x5 << 23; @@ -112,29 +112,17 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) struct drm_i915_gem_exec_object2 obj; struct drm_i915_gem_relocation_entry reloc[4], *r; uint32_t *bbe[2], *state, *batch; - unsigned engines[16], nengine, flags; struct timespec tv = {}; unsigned long cycles; + unsigned flags; uint64_t elapsed; flags = I915_EXEC_NO_RELOC; if (gen == 4 || gen == 5) flags |= I915_EXEC_SECURE; - nengine = 0; - if (ring == ALL_ENGINES) { - for_each_physical_engine(fd, ring) { - if (!gem_can_store_dword(fd, ring)) - continue; - - engines[nengine++] = ring; - } - } else { - gem_require_ring(fd, ring); - igt_require(gem_can_store_dword(fd, ring)); - engines[nengine++] = ring; - } - igt_require(nengine); + gem_require_ring(fd, engine); + igt_require(gem_can_store_dword(fd, engine)); memset(&obj, 0, sizeof(obj)); obj.handle = gem_create(fd, 4096); @@ -198,7 +186,7 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = to_user_pointer(&obj); execbuf.buffer_count = 1; - execbuf.flags = engines[0]; + execbuf.flags = engine | flags; cycles = 0; do { @@ -208,7 +196,6 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) execbuf.batch_start_offset = (bbe[idx] - batch) * sizeof(*batch) - 64; - execbuf.flags = engines[cycles % nengine] | flags; gem_execbuf(fd, &execbuf); *bbe[!idx] = MI_BATCH_BUFFER_END; @@ -227,6 +214,133 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) gem_close(fd, obj.handle); } +static void poll_sequential(int fd, const char *name, int timeout) +{ + const int gen = intel_gen(intel_get_drm_devid(fd)); + const uint32_t MI_ARB_CHK = 0x5 << 23; + struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_exec_object2 obj[2]; + struct drm_i915_gem_relocation_entry reloc[4], *r; + uint32_t *bbe[2], *state, *batch; + unsigned engines[16], nengine, engine, flags; + struct timespec tv = {}; + unsigned long cycles; + uint64_t elapsed; + bool cached; + + flags = I915_EXEC_NO_RELOC; + if (gen == 4 || gen == 5) + flags |= I915_EXEC_SECURE; + + nengine = 0; + for_each_physical_engine(fd, engine) { + if (!gem_can_store_dword(fd, engine)) + continue; + + engines[nengine++] = engine; + } + igt_require(nengine); + + memset(obj, 0, sizeof(obj)); + obj[0].handle = gem_create(fd, 4096); + obj[0].flags = EXEC_OBJECT_WRITE; + cached = __gem_set_caching(fd, obj[0].handle, 1) == 0; + obj[1].handle = gem_create(fd, 4096); + obj[1].relocs_ptr = to_user_pointer(reloc); + obj[1].relocation_count = ARRAY_SIZE(reloc); + + r = memset(reloc, 0, sizeof(reloc)); + batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE); + + for (unsigned int start_offset = 0; + start_offset <= 128; + start_offset += 128) { + uint32_t *b = batch + start_offset / sizeof(*batch); + + r->target_handle = obj[0].handle; + r->offset = (b - batch + 1) * sizeof(uint32_t); + r->delta = 0; + r->read_domains = I915_GEM_DOMAIN_RENDER; + r->write_domain = I915_GEM_DOMAIN_RENDER; + + *b = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); + if (gen >= 8) { + *++b = r->delta; + *++b = 0; + } else if (gen >= 4) { + r->offset += sizeof(uint32_t); + *++b = 0; + *++b = r->delta; + } else { + *b -= 1; + *++b = r->delta; + } + *++b = start_offset != 0; + r++; + + b = batch + (start_offset + 64) / sizeof(*batch); + bbe[start_offset != 0] = b; + *b++ = MI_ARB_CHK; + + r->target_handle = obj[1].handle; + r->offset = (b - batch + 1) * sizeof(uint32_t); + r->read_domains = I915_GEM_DOMAIN_COMMAND; + r->delta = start_offset + 64; + if (gen >= 8) { + *b++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; + *b++ = r->delta; + *b++ = 0; + } else if (gen >= 6) { + *b++ = MI_BATCH_BUFFER_START | 1 << 8; + *b++ = r->delta; + } else { + *b++ = MI_BATCH_BUFFER_START | 2 << 6; + if (gen < 4) + r->delta |= 1; + *b++ = r->delta; + } + r++; + } + igt_assert(r == reloc + ARRAY_SIZE(reloc)); + + if (cached) + state = gem_mmap__cpu(fd, obj[0].handle, 0, 4096, PROT_READ); + else + state = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_READ); + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.buffer_count = ARRAY_SIZE(obj); + + cycles = 0; + do { + unsigned int idx = ++cycles & 1; + + *bbe[idx] = MI_ARB_CHK; + execbuf.batch_start_offset = + (bbe[idx] - batch) * sizeof(*batch) - 64; + + execbuf.flags = engines[cycles % nengine] | flags; + gem_execbuf(fd, &execbuf); + + *bbe[!idx] = MI_BATCH_BUFFER_END; + __sync_synchronize(); + + while (READ_ONCE(*state) != idx) + ; + } while ((elapsed = igt_nsec_elapsed(&tv)) >> 30 < timeout); + *bbe[cycles & 1] = MI_BATCH_BUFFER_END; + gem_sync(fd, obj[1].handle); + + igt_info("%s completed %ld cycles: %.3f us\n", + name, cycles, elapsed*1e-3/cycles); + + munmap(state, 4096); + munmap(batch, 4096); + gem_close(fd, obj[1].handle); + gem_close(fd, obj[0].handle); +} + static void single(int fd, uint32_t handle, unsigned ring_id, const char *ring_name) { @@ -813,7 +927,7 @@ igt_main } igt_subtest("poll-sequential") - poll_ring(device, ALL_ENGINES, "Sequential", 20); + poll_sequential(device, "Sequential", 20); igt_subtest("headless") { /* Requires master for changing display modes */ -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Subject: [igt-dev] [PATCH i-g-t 06/24] i915/gem_exec_nop: poll-sequential requires ordering between rings Date: Fri, 22 Mar 2019 09:21:37 +0000 [thread overview] Message-ID: <20190322092155.1656-6-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20190322092155.1656-1-chris@chris-wilson.co.uk> In order to correctly serialise the order of execution between rings, we need to flag the scratch address as being written. Make it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- tests/i915/gem_exec_nop.c | 152 +++++++++++++++++++++++++++++++++----- 1 file changed, 133 insertions(+), 19 deletions(-) diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c index 59a08ad08..b91b4d0f6 100644 --- a/tests/i915/gem_exec_nop.c +++ b/tests/i915/gem_exec_nop.c @@ -104,7 +104,7 @@ static double nop_on_ring(int fd, uint32_t handle, unsigned ring_id, return elapsed(&start, &now); } -static void poll_ring(int fd, unsigned ring, const char *name, int timeout) +static void poll_ring(int fd, unsigned engine, const char *name, int timeout) { const int gen = intel_gen(intel_get_drm_devid(fd)); const uint32_t MI_ARB_CHK = 0x5 << 23; @@ -112,29 +112,17 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) struct drm_i915_gem_exec_object2 obj; struct drm_i915_gem_relocation_entry reloc[4], *r; uint32_t *bbe[2], *state, *batch; - unsigned engines[16], nengine, flags; struct timespec tv = {}; unsigned long cycles; + unsigned flags; uint64_t elapsed; flags = I915_EXEC_NO_RELOC; if (gen == 4 || gen == 5) flags |= I915_EXEC_SECURE; - nengine = 0; - if (ring == ALL_ENGINES) { - for_each_physical_engine(fd, ring) { - if (!gem_can_store_dword(fd, ring)) - continue; - - engines[nengine++] = ring; - } - } else { - gem_require_ring(fd, ring); - igt_require(gem_can_store_dword(fd, ring)); - engines[nengine++] = ring; - } - igt_require(nengine); + gem_require_ring(fd, engine); + igt_require(gem_can_store_dword(fd, engine)); memset(&obj, 0, sizeof(obj)); obj.handle = gem_create(fd, 4096); @@ -198,7 +186,7 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = to_user_pointer(&obj); execbuf.buffer_count = 1; - execbuf.flags = engines[0]; + execbuf.flags = engine | flags; cycles = 0; do { @@ -208,7 +196,6 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) execbuf.batch_start_offset = (bbe[idx] - batch) * sizeof(*batch) - 64; - execbuf.flags = engines[cycles % nengine] | flags; gem_execbuf(fd, &execbuf); *bbe[!idx] = MI_BATCH_BUFFER_END; @@ -227,6 +214,133 @@ static void poll_ring(int fd, unsigned ring, const char *name, int timeout) gem_close(fd, obj.handle); } +static void poll_sequential(int fd, const char *name, int timeout) +{ + const int gen = intel_gen(intel_get_drm_devid(fd)); + const uint32_t MI_ARB_CHK = 0x5 << 23; + struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_exec_object2 obj[2]; + struct drm_i915_gem_relocation_entry reloc[4], *r; + uint32_t *bbe[2], *state, *batch; + unsigned engines[16], nengine, engine, flags; + struct timespec tv = {}; + unsigned long cycles; + uint64_t elapsed; + bool cached; + + flags = I915_EXEC_NO_RELOC; + if (gen == 4 || gen == 5) + flags |= I915_EXEC_SECURE; + + nengine = 0; + for_each_physical_engine(fd, engine) { + if (!gem_can_store_dword(fd, engine)) + continue; + + engines[nengine++] = engine; + } + igt_require(nengine); + + memset(obj, 0, sizeof(obj)); + obj[0].handle = gem_create(fd, 4096); + obj[0].flags = EXEC_OBJECT_WRITE; + cached = __gem_set_caching(fd, obj[0].handle, 1) == 0; + obj[1].handle = gem_create(fd, 4096); + obj[1].relocs_ptr = to_user_pointer(reloc); + obj[1].relocation_count = ARRAY_SIZE(reloc); + + r = memset(reloc, 0, sizeof(reloc)); + batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE); + + for (unsigned int start_offset = 0; + start_offset <= 128; + start_offset += 128) { + uint32_t *b = batch + start_offset / sizeof(*batch); + + r->target_handle = obj[0].handle; + r->offset = (b - batch + 1) * sizeof(uint32_t); + r->delta = 0; + r->read_domains = I915_GEM_DOMAIN_RENDER; + r->write_domain = I915_GEM_DOMAIN_RENDER; + + *b = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); + if (gen >= 8) { + *++b = r->delta; + *++b = 0; + } else if (gen >= 4) { + r->offset += sizeof(uint32_t); + *++b = 0; + *++b = r->delta; + } else { + *b -= 1; + *++b = r->delta; + } + *++b = start_offset != 0; + r++; + + b = batch + (start_offset + 64) / sizeof(*batch); + bbe[start_offset != 0] = b; + *b++ = MI_ARB_CHK; + + r->target_handle = obj[1].handle; + r->offset = (b - batch + 1) * sizeof(uint32_t); + r->read_domains = I915_GEM_DOMAIN_COMMAND; + r->delta = start_offset + 64; + if (gen >= 8) { + *b++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; + *b++ = r->delta; + *b++ = 0; + } else if (gen >= 6) { + *b++ = MI_BATCH_BUFFER_START | 1 << 8; + *b++ = r->delta; + } else { + *b++ = MI_BATCH_BUFFER_START | 2 << 6; + if (gen < 4) + r->delta |= 1; + *b++ = r->delta; + } + r++; + } + igt_assert(r == reloc + ARRAY_SIZE(reloc)); + + if (cached) + state = gem_mmap__cpu(fd, obj[0].handle, 0, 4096, PROT_READ); + else + state = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_READ); + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.buffer_count = ARRAY_SIZE(obj); + + cycles = 0; + do { + unsigned int idx = ++cycles & 1; + + *bbe[idx] = MI_ARB_CHK; + execbuf.batch_start_offset = + (bbe[idx] - batch) * sizeof(*batch) - 64; + + execbuf.flags = engines[cycles % nengine] | flags; + gem_execbuf(fd, &execbuf); + + *bbe[!idx] = MI_BATCH_BUFFER_END; + __sync_synchronize(); + + while (READ_ONCE(*state) != idx) + ; + } while ((elapsed = igt_nsec_elapsed(&tv)) >> 30 < timeout); + *bbe[cycles & 1] = MI_BATCH_BUFFER_END; + gem_sync(fd, obj[1].handle); + + igt_info("%s completed %ld cycles: %.3f us\n", + name, cycles, elapsed*1e-3/cycles); + + munmap(state, 4096); + munmap(batch, 4096); + gem_close(fd, obj[1].handle); + gem_close(fd, obj[0].handle); +} + static void single(int fd, uint32_t handle, unsigned ring_id, const char *ring_name) { @@ -813,7 +927,7 @@ igt_main } igt_subtest("poll-sequential") - poll_ring(device, ALL_ENGINES, "Sequential", 20); + poll_sequential(device, "Sequential", 20); igt_subtest("headless") { /* Requires master for changing display modes */ -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev
next prev parent reply other threads:[~2019-03-22 9:21 UTC|newest] Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-22 9:21 [PATCH i-g-t 01/24] i915/gem_exec_latency: Measure the latency of context switching Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 02/24] lib: Add GPU power measurement Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 8:36 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 8:36 ` Tvrtko Ursulin 2019-03-26 8:49 ` Chris Wilson 2019-03-26 8:49 ` Chris Wilson 2019-03-26 9:18 ` [PATCH i-g-t v2] " Chris Wilson 2019-03-26 9:18 ` [igt-dev] " Chris Wilson 2019-03-26 9:52 ` Tvrtko Ursulin 2019-03-26 9:52 ` Tvrtko Ursulin 2019-03-26 10:06 ` Chris Wilson 2019-03-26 10:06 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 03/24] i915/gem_exec_schedule: Measure semaphore power consumption Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 8:46 ` Tvrtko Ursulin 2019-03-26 8:46 ` [Intel-gfx] " Tvrtko Ursulin 2019-03-26 9:23 ` Chris Wilson 2019-03-26 9:23 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 04/24] i915/gem_exec_whisper: Measure total power consumed Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 8:47 ` Tvrtko Ursulin 2019-03-26 8:47 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 05/24] i915/gem_exec_schedule: Verify that using HW semaphores doesn't block Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 9:19 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 9:19 ` Tvrtko Ursulin 2019-03-26 10:03 ` Chris Wilson 2019-03-26 10:03 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` Chris Wilson [this message] 2019-03-22 9:21 ` [igt-dev] [PATCH i-g-t 06/24] i915/gem_exec_nop: poll-sequential requires ordering between rings Chris Wilson 2019-03-26 9:38 ` Tvrtko Ursulin 2019-03-26 9:38 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 07/24] i915/gem_sync: Make switch-default asymmetric Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 9:57 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 9:57 ` [Intel-gfx] " Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 08/24] i915/gem_ctx_param: Remove kneecapping Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 9:58 ` Tvrtko Ursulin 2019-03-26 9:58 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 09/24] i915/gem_exec_big: Add a single shot test Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-26 10:06 ` [igt-dev] " Tvrtko Ursulin 2019-03-26 10:06 ` Tvrtko Ursulin 2019-03-26 10:21 ` Chris Wilson 2019-03-26 10:21 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 10/24] kms_fence_pin_leak: Ask for the GPU before use Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:10 ` Tvrtko Ursulin 2019-03-26 10:10 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 11/24] drm-uapi: Import i915_drm.h upto 53073249452d Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 12/24] lib/i915: Improve gem_context error messages Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:14 ` Tvrtko Ursulin 2019-03-26 10:14 ` Tvrtko Ursulin 2019-03-22 9:21 ` [PATCH i-g-t 13/24] i915/gem_ctx_param: Test set/get (copy) VM Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:22 ` Tvrtko Ursulin 2019-03-26 10:22 ` Tvrtko Ursulin 2019-03-26 10:33 ` Tvrtko Ursulin 2019-03-26 10:33 ` Tvrtko Ursulin 2019-03-26 10:51 ` Chris Wilson 2019-03-26 10:51 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 14/24] i915/gem_ctx_create: Basic checks for constructor properties Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 10:46 ` Tvrtko Ursulin 2019-03-26 10:46 ` Tvrtko Ursulin 2019-03-26 11:06 ` Chris Wilson 2019-03-26 11:06 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 15/24] i915: Add gem_vm_create Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 11:21 ` Tvrtko Ursulin 2019-03-26 11:21 ` Tvrtko Ursulin 2019-03-26 11:37 ` Chris Wilson 2019-03-26 11:37 ` Chris Wilson 2019-03-26 11:48 ` Tvrtko Ursulin 2019-03-26 11:48 ` Tvrtko Ursulin 2019-03-26 14:11 ` Chris Wilson 2019-03-26 14:11 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 16/24] drm-uapi: Import i915_drm.h upto 364df3d04d51 Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 17/24] i915: Add gem_ctx_clone Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-26 15:44 ` Tvrtko Ursulin 2019-03-26 15:44 ` Tvrtko Ursulin 2019-03-26 15:49 ` Chris Wilson 2019-03-26 15:49 ` Chris Wilson 2019-03-26 15:54 ` Chris Wilson 2019-03-26 15:54 ` Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 18/24] i915: Exercise creating context with shared GTT Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 19/24] i915/gem_ctx_switch: Exercise queues Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 20/24] i915/gem_exec_whisper: Fork all-engine tests one-per-engine Chris Wilson 2019-03-22 9:21 ` [Intel-gfx] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 21/24] i915/gem_exec_whisper: debugfs/next_seqno is defunct Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 22/24] i915: Add gem_ctx_engines Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 16:40 ` Andi Shyti 2019-03-22 16:40 ` [igt-dev] " Andi Shyti 2019-03-22 16:48 ` Chris Wilson 2019-03-22 16:48 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 23/24] i915: Add gem_exec_balancer Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 9:21 ` [PATCH i-g-t 24/24] i915/gem_exec_balancer: Exercise bonded pairs Chris Wilson 2019-03-22 9:21 ` [igt-dev] " Chris Wilson 2019-03-22 10:22 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,01/24] i915/gem_exec_latency: Measure the latency of context switching Patchwork 2019-03-23 6:38 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2019-03-26 11:00 ` [igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,01/24] i915/gem_exec_latency: Measure the latency of context switching (rev2) Patchwork
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