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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Jingoo Han <jingoohan1@gmail.com>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-omap@vger.kernel.org>,
	<linux-rockchip@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Kishon Vijay Abraham I <kishon@ti.com>
Subject: [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC
Date: Tue, 4 Jun 2019 18:44:54 +0530	[thread overview]
Message-ID: <20190604131516.13596-9-kishon@ti.com> (raw)
In-Reply-To: <20190604131516.13596-1-kishon@ti.com>

Use J721E specific compatible in pcie-cadence-* drivers. Since PCIe in
J721E SoC has a restriction that allows only 32-bit register access,
use the 32-bit accessors for read and write.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   | 12 +++++-
 drivers/pci/controller/pcie-cadence-host.c | 47 +++++++++++++++++++++-
 2 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 64ab5c53afb1..07f840cfba23 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -425,9 +425,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
 	.get_features	= cdns_pcie_ep_get_features,
 };
 
-static const struct of_device_id cdns_pcie_ep_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-ep" },
+static struct cdns_pcie_ep_data cdns_ti_pcie_ep_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+};
 
+static const struct of_device_id cdns_pcie_ep_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-ep",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-ep",
+	  .data = &cdns_ti_pcie_ep_data,
+	},
 	{ },
 };
 
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index 75cf3c312ed2..ab6491b23775 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -93,9 +93,52 @@ static struct pci_ops cdns_pcie_host_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static const struct of_device_id cdns_pcie_host_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-host" },
+static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+				    int where, int size, u32 *value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_read32(bus, devfn, where, size,
+						 value);
+
+	return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
+				     int where, int size, u32 value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_write32(bus, devfn, where, size,
+						  value);
+
+	return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
+static struct pci_ops cdns_ti_pcie_host_ops = {
+	.map_bus	= cdns_pci_map_bus,
+	.read		= cdns_ti_pcie_config_read,
+	.write		= cdns_ti_pcie_config_write,
+};
+
+static struct cdns_pcie_host_data cdns_ti_pcie_host_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+	.ops = &cdns_ti_pcie_host_ops,
+};
 
+static const struct of_device_id cdns_pcie_host_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-host",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-host",
+	  .data = &cdns_ti_pcie_host_data,
+	},
 	{ },
 };
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Kishon Vijay Abraham I <kishon@ti.com>
Subject: [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC
Date: Tue, 4 Jun 2019 18:44:54 +0530	[thread overview]
Message-ID: <20190604131516.13596-9-kishon@ti.com> (raw)
In-Reply-To: <20190604131516.13596-1-kishon@ti.com>

Use J721E specific compatible in pcie-cadence-* drivers. Since PCIe in
J721E SoC has a restriction that allows only 32-bit register access,
use the 32-bit accessors for read and write.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   | 12 +++++-
 drivers/pci/controller/pcie-cadence-host.c | 47 +++++++++++++++++++++-
 2 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 64ab5c53afb1..07f840cfba23 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -425,9 +425,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
 	.get_features	= cdns_pcie_ep_get_features,
 };
 
-static const struct of_device_id cdns_pcie_ep_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-ep" },
+static struct cdns_pcie_ep_data cdns_ti_pcie_ep_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+};
 
+static const struct of_device_id cdns_pcie_ep_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-ep",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-ep",
+	  .data = &cdns_ti_pcie_ep_data,
+	},
 	{ },
 };
 
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index 75cf3c312ed2..ab6491b23775 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -93,9 +93,52 @@ static struct pci_ops cdns_pcie_host_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static const struct of_device_id cdns_pcie_host_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-host" },
+static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+				    int where, int size, u32 *value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_read32(bus, devfn, where, size,
+						 value);
+
+	return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
+				     int where, int size, u32 value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_write32(bus, devfn, where, size,
+						  value);
+
+	return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
+static struct pci_ops cdns_ti_pcie_host_ops = {
+	.map_bus	= cdns_pci_map_bus,
+	.read		= cdns_ti_pcie_config_read,
+	.write		= cdns_ti_pcie_config_write,
+};
+
+static struct cdns_pcie_host_data cdns_ti_pcie_host_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+	.ops = &cdns_ti_pcie_host_ops,
+};
 
+static const struct of_device_id cdns_pcie_host_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-host",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-host",
+	  .data = &cdns_ti_pcie_host_data,
+	},
 	{ },
 };
 
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, Jingoo Han <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Kishon Vijay Abraham I <kishon@ti.com>,
	linux-rockchip@lists.infradead.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-omap@vger.kernel.org, Frank Rowand <frowand.list@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC
Date: Tue, 4 Jun 2019 18:44:54 +0530	[thread overview]
Message-ID: <20190604131516.13596-9-kishon@ti.com> (raw)
In-Reply-To: <20190604131516.13596-1-kishon@ti.com>

Use J721E specific compatible in pcie-cadence-* drivers. Since PCIe in
J721E SoC has a restriction that allows only 32-bit register access,
use the 32-bit accessors for read and write.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/pcie-cadence-ep.c   | 12 +++++-
 drivers/pci/controller/pcie-cadence-host.c | 47 +++++++++++++++++++++-
 2 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 64ab5c53afb1..07f840cfba23 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -425,9 +425,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
 	.get_features	= cdns_pcie_ep_get_features,
 };
 
-static const struct of_device_id cdns_pcie_ep_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-ep" },
+static struct cdns_pcie_ep_data cdns_ti_pcie_ep_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+};
 
+static const struct of_device_id cdns_pcie_ep_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-ep",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-ep",
+	  .data = &cdns_ti_pcie_ep_data,
+	},
 	{ },
 };
 
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index 75cf3c312ed2..ab6491b23775 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -93,9 +93,52 @@ static struct pci_ops cdns_pcie_host_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static const struct of_device_id cdns_pcie_host_of_match[] = {
-	{ .compatible = "cdns,cdns-pcie-host" },
+static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+				    int where, int size, u32 *value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_read32(bus, devfn, where, size,
+						 value);
+
+	return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
+				     int where, int size, u32 value)
+{
+	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+	struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+	unsigned int busn = bus->number;
+
+	if (busn == rc->bus_range->start)
+		return pci_generic_config_write32(bus, devfn, where, size,
+						  value);
+
+	return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
+static struct pci_ops cdns_ti_pcie_host_ops = {
+	.map_bus	= cdns_pci_map_bus,
+	.read		= cdns_ti_pcie_config_read,
+	.write		= cdns_ti_pcie_config_write,
+};
+
+static struct cdns_pcie_host_data cdns_ti_pcie_host_data = {
+	.read = cdns_pcie_read32,
+	.write = cdns_pcie_write32,
+	.ops = &cdns_ti_pcie_host_ops,
+};
 
+static const struct of_device_id cdns_pcie_host_of_match[] = {
+	{ .compatible = "cdns,cdns-pcie-host",
+	},
+	{ .compatible = "ti,j721e-cdns-pcie-host",
+	  .data = &cdns_ti_pcie_host_data,
+	},
 	{ },
 };
 
-- 
2.17.1


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  parent reply	other threads:[~2019-06-04 13:18 UTC|newest]

Thread overview: 104+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-04 13:14 [RFC PATCH 00/30] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-06-04 13:14 ` Kishon Vijay Abraham I
2019-06-04 13:14 ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 01/30] dt-bindings: PCI: cadence: Add DT binding to use PCIe with IOMMU Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 02/30] dt-bindings: PCI: cadence: Add binding to reset PERST# Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 03/30] dt-bindings: PCI: cadence: Update host DT bindings with TI specific compatible Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 04/30] dt-bindings: PCI: cadence: Update EP " Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 05/30] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 06/30] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 07/30] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` Kishon Vijay Abraham I [this message]
2019-06-04 13:14   ` [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 09/30] PCI: cadence: Add platform_data to start link and check link status Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 10/30] PCI: cadence: Use *_start_link() and *_wait_for_link() to establish link Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 11/30] PCI: cadence: Add support to drive PERST# line using GPIO Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 12/30] PCI: cadence: Make "mem" an optional memory resource Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 13/30] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:14   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 14/30] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 15/30] PCI: endpoint: Replace spinlock with mutex Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 16/30] PCI: endpoint: Assign function number of each PF in EPC core Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 17/30] PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 18/30] PCI: endpoint: Add support to add virtual function in endpoint core Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 19/30] PCI: endpoint: Add support to link a physical function to a virtual function Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 20/30] PCI: endpoint: Add virtual function number in pci_epc ops Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 21/30] PCI: cadence: Add support to configure virtual functions Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 22/30] PCI: cadence: Configure pci_epc_features to align BAR addresses to 256 Bytes Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 23/30] of/platform: Export of_platform_device_create_pdata() Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-10 17:43   ` Rob Herring
2019-06-10 17:43     ` Rob Herring
2019-06-10 17:43     ` Rob Herring
2019-06-11  4:38     ` Kishon Vijay Abraham I
2019-06-11  4:38       ` Kishon Vijay Abraham I
2019-06-11  4:38       ` Kishon Vijay Abraham I
2019-07-19 10:55       ` Kishon Vijay Abraham I
2019-07-19 10:55         ` Kishon Vijay Abraham I
2019-07-19 10:55         ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 24/30] dt-bindings: PCI: J721E: Add DT bindings for PCIe controller in J721E Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 25/30] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 26/30] MAINTAINERS: Add MAINTAINER entry for PCIe on TI's J721E SoC Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 19:45   ` Bjorn Helgaas
2019-06-04 19:45     ` Bjorn Helgaas
2019-06-04 13:15 ` [RFC PATCH 27/30] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 28/30] misc: pci_endpoint_test: Avoid using module parameter to determine irqtype Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 29/30] misc: pci_endpoint_test: Populate sriov_configure ops to configure SRIOV device Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 30/30] misc: pci_endpoint_test: Enable legacy interrupt Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I
2019-06-04 13:15   ` Kishon Vijay Abraham I

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