From: Miquel Raynal <miquel.raynal@bootlin.com> To: Mark Brown <broonie@kernel.org>, Michal Simek <michal.simek@xilinx.com>, Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, linux-spi@vger.kernel.org Subject: [PATCH v2 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions Date: Fri, 8 Nov 2019 15:07:41 +0100 [thread overview] Message-ID: <20191108140744.1734-5-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20191108140744.1734-1-miquel.raynal@bootlin.com> Using masks makes sense when manipulating fields of several bits. When only one bit is involved, it is usual to just use the BIT() macro but in this case using the term mask is abusive. Fix the #define macros and their comments. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/spi/spi-zynq-qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 78711fe955f4..1151443ec830 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -99,9 +99,9 @@ * It is named Linear Configuration but it controls other modes when not in * linear mode also. */ -#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK BIT(30) /* LQSPI Two memories Mask */ -#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK BIT(29) /* LQSPI Separate bus Mask */ -#define ZYNQ_QSPI_LCFG_U_PAGE_MASK BIT(28) /* LQSPI Upper Page Mask */ +#define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */ +#define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */ +#define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */ #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com> To: Mark Brown <broonie@kernel.org>, Michal Simek <michal.simek@xilinx.com>, Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, linux-spi@vger.kernel.org Subject: [PATCH v2 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions Date: Fri, 8 Nov 2019 15:07:41 +0100 [thread overview] Message-ID: <20191108140744.1734-5-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20191108140744.1734-1-miquel.raynal@bootlin.com> Using masks makes sense when manipulating fields of several bits. When only one bit is involved, it is usual to just use the BIT() macro but in this case using the term mask is abusive. Fix the #define macros and their comments. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/spi/spi-zynq-qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 78711fe955f4..1151443ec830 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -99,9 +99,9 @@ * It is named Linear Configuration but it controls other modes when not in * linear mode also. */ -#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK BIT(30) /* LQSPI Two memories Mask */ -#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK BIT(29) /* LQSPI Separate bus Mask */ -#define ZYNQ_QSPI_LCFG_U_PAGE_MASK BIT(28) /* LQSPI Upper Page Mask */ +#define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */ +#define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */ +#define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */ #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-08 14:07 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-08 14:07 [PATCH v2 0/7] spi: zynq-qspi: Clarify and fix the chip selection Miquel Raynal 2019-11-08 14:07 ` [PATCH v2 1/7] spi: zynq-qspi: Anything else than CS0 is not supported yet Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Anything else than CS0 is not supported yet" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown 2019-11-08 14:07 ` [PATCH v2 2/7] spi: zynq-qspi: Keep the naming consistent across the driver Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 14:07 ` [PATCH v2 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Keep the bitfields naming consistent" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown 2019-11-08 14:07 ` Miquel Raynal [this message] 2019-11-08 14:07 ` [PATCH v2 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Enhance the Linear CFG bit definitions" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown 2019-11-08 14:07 ` [PATCH v2 5/7] spi: zynq-qspi: Clarify the select chip function Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Clarify the select chip function" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown 2019-11-08 14:07 ` [PATCH v2 6/7] spi: zynq-qspi: Do the actual hardware initialization later in the probe Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Do the actual hardware initialization later in the probe" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown 2019-11-08 14:07 ` [PATCH v2 7/7] spi: zynq-qspi: Support two chip selects Miquel Raynal 2019-11-08 14:07 ` Miquel Raynal 2019-11-08 17:45 ` Applied "spi: zynq-qspi: Support two chip selects" to the spi tree Mark Brown 2019-11-08 17:45 ` Mark Brown
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