From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<cui.zhang@mediatek.com>, <chao.hao@mediatek.com>,
<ming-fan.chen@mediatek.com>
Subject: [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Sat, 11 Jul 2020 14:48:34 +0800 [thread overview]
Message-ID: <20200711064846.16007-10-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
The standard input iova bits is 32. MediaTek quad the lvl1
pagetable(4*lvl1). No change for lvl2 pagetable.
Then the iova bits can reach 34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 10 +++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index e1c98be61e1b..cad314a92abc 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,14 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (!arm_v7s_is_mtk_enabled(cfg) ?\
+ (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl)))
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +67,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -756,7 +760,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c3b4d21760ed..a6412d454e0b 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com,
anan.sun@mediatek.com, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Sat, 11 Jul 2020 14:48:34 +0800 [thread overview]
Message-ID: <20200711064846.16007-10-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
The standard input iova bits is 32. MediaTek quad the lvl1
pagetable(4*lvl1). No change for lvl2 pagetable.
Then the iova bits can reach 34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 10 +++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index e1c98be61e1b..cad314a92abc 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,14 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (!arm_v7s_is_mtk_enabled(cfg) ?\
+ (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl)))
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +67,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -756,7 +760,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c3b4d21760ed..a6412d454e0b 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Sat, 11 Jul 2020 14:48:34 +0800 [thread overview]
Message-ID: <20200711064846.16007-10-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
The standard input iova bits is 32. MediaTek quad the lvl1
pagetable(4*lvl1). No change for lvl2 pagetable.
Then the iova bits can reach 34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 10 +++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index e1c98be61e1b..cad314a92abc 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,14 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (!arm_v7s_is_mtk_enabled(cfg) ?\
+ (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl)))
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +67,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -756,7 +760,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c3b4d21760ed..a6412d454e0b 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Sat, 11 Jul 2020 14:48:34 +0800 [thread overview]
Message-ID: <20200711064846.16007-10-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
The standard input iova bits is 32. MediaTek quad the lvl1
pagetable(4*lvl1). No change for lvl2 pagetable.
Then the iova bits can reach 34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 10 +++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index e1c98be61e1b..cad314a92abc 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,14 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (!arm_v7s_is_mtk_enabled(cfg) ?\
+ (1 << _ARM_V7S_LVL_BITS(lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(lvl)))
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +67,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -756,7 +760,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c3b4d21760ed..a6412d454e0b 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-11 6:51 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 6:48 [PATCH 00/21] MT8192 IOMMU support Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:27 ` [SPAM]Re: " Yong Wu
2020-07-13 6:27 ` Yong Wu
2020-07-13 6:27 ` Yong Wu
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-11 6:48 ` [PATCH 02/21] dt-binding: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-11 6:48 ` [PATCH 03/21] dt-binding: memory: mediatek: Add domain definition Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-11 6:48 ` [PATCH 05/21] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 06/21] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-11 6:48 ` [PATCH 07/21] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 08/21] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu [this message]
2020-07-11 6:48 ` [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 10/21] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 11/21] iommu/mediatek: Add power-domain operation Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-07-11 6:48 ` [PATCH 12/21] iommu/mediatek: Add iova reserved function Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-11 6:48 ` [PATCH 13/21] iommu/mediatek: Make MTK_IOMMU depend on ARM64 Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 14/21] iommu/mediatek: Add single domain Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 15/21] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 16/21] iommu/mediatek: Support up to 34bit iova in tlb invalid Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 18/21] iommu/mediatek: Add support for multi domain Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-11 6:48 ` [PATCH 19/21] iommu/mediatek: Adjust the structure Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 20/21] iommu/mediatek: Add mt8192 support Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 21/21] memory: mtk-smi: " Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
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