From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<cui.zhang@mediatek.com>, <chao.hao@mediatek.com>,
<ming-fan.chen@mediatek.com>
Subject: [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR
Date: Sat, 11 Jul 2020 14:48:42 +0800 [thread overview]
Message-ID: <20200711064846.16007-18-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c6649a97bd7..766c9e73d541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -4,6 +4,7 @@
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#include <linux/memblock.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/component.h>
@@ -87,6 +88,9 @@
#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
#define REG_MMU0_FAULT_VA 0x13c
+#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
+#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
+#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -110,6 +114,7 @@
#define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6)
+#define IOVA_34_EN BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -269,8 +274,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
- u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
+ u32 int_state, regval, va34_32, pa34_32;
+ u64 fault_iova, fault_pa;
bool layer, write;
/* Read error info from registers */
@@ -286,6 +292,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
+ va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
+ pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
+ fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
+ fault_iova |= (u64)va34_32 << 32;
+ fault_pa |= (u64)pa34_32 << 32;
+ }
+
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
@@ -299,7 +313,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
+ "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
int_state, fault_iova, fault_pa, fault_larb, fault_port,
layer, write ? "write" : "read");
}
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com,
anan.sun@mediatek.com, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR
Date: Sat, 11 Jul 2020 14:48:42 +0800 [thread overview]
Message-ID: <20200711064846.16007-18-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c6649a97bd7..766c9e73d541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -4,6 +4,7 @@
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#include <linux/memblock.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/component.h>
@@ -87,6 +88,9 @@
#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
#define REG_MMU0_FAULT_VA 0x13c
+#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
+#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
+#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -110,6 +114,7 @@
#define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6)
+#define IOVA_34_EN BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -269,8 +274,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
- u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
+ u32 int_state, regval, va34_32, pa34_32;
+ u64 fault_iova, fault_pa;
bool layer, write;
/* Read error info from registers */
@@ -286,6 +292,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
+ va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
+ pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
+ fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
+ fault_iova |= (u64)va34_32 << 32;
+ fault_pa |= (u64)pa34_32 << 32;
+ }
+
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
@@ -299,7 +313,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
+ "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
int_state, fault_iova, fault_pa, fault_larb, fault_port,
layer, write ? "write" : "read");
}
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR
Date: Sat, 11 Jul 2020 14:48:42 +0800 [thread overview]
Message-ID: <20200711064846.16007-18-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c6649a97bd7..766c9e73d541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -4,6 +4,7 @@
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#include <linux/memblock.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/component.h>
@@ -87,6 +88,9 @@
#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
#define REG_MMU0_FAULT_VA 0x13c
+#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
+#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
+#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -110,6 +114,7 @@
#define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6)
+#define IOVA_34_EN BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -269,8 +274,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
- u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
+ u32 int_state, regval, va34_32, pa34_32;
+ u64 fault_iova, fault_pa;
bool layer, write;
/* Read error info from registers */
@@ -286,6 +292,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
+ va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
+ pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
+ fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
+ fault_iova |= (u64)va34_32 << 32;
+ fault_pa |= (u64)pa34_32 << 32;
+ }
+
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
@@ -299,7 +313,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
+ "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
int_state, fault_iova, fault_pa, fault_larb, fault_port,
layer, write ? "write" : "read");
}
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR
Date: Sat, 11 Jul 2020 14:48:42 +0800 [thread overview]
Message-ID: <20200711064846.16007-18-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c6649a97bd7..766c9e73d541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -4,6 +4,7 @@
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#include <linux/memblock.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/component.h>
@@ -87,6 +88,9 @@
#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
#define REG_MMU0_FAULT_VA 0x13c
+#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
+#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
+#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -110,6 +114,7 @@
#define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6)
+#define IOVA_34_EN BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -269,8 +274,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
- u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
+ u32 int_state, regval, va34_32, pa34_32;
+ u64 fault_iova, fault_pa;
bool layer, write;
/* Read error info from registers */
@@ -286,6 +292,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
+ va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
+ pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
+ fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
+ fault_iova |= (u64)va34_32 << 32;
+ fault_pa |= (u64)pa34_32 << 32;
+ }
+
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
@@ -299,7 +313,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
+ "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
int_state, fault_iova, fault_pa, fault_larb, fault_port,
layer, write ? "write" : "read");
}
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-11 6:52 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 6:48 [PATCH 00/21] MT8192 IOMMU support Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-12 18:06 ` Matthias Brugger
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 5:43 ` Pi-Hsun Shih
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:28 ` Yong Wu
2020-07-13 6:27 ` [SPAM]Re: " Yong Wu
2020-07-13 6:27 ` Yong Wu
2020-07-13 6:27 ` Yong Wu
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-20 22:58 ` Rob Herring
2020-07-11 6:48 ` [PATCH 02/21] dt-binding: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-20 22:59 ` Rob Herring
2020-07-11 6:48 ` [PATCH 03/21] dt-binding: memory: mediatek: Add domain definition Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 5:36 ` Pi-Hsun Shih
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-13 6:54 ` Yong Wu
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-20 23:16 ` Rob Herring
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-21 3:27 ` Yong Wu
2020-07-11 6:48 ` [PATCH 05/21] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 06/21] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 0:38 ` Nicolas Boichat
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-13 6:52 ` Yong Wu
2020-07-11 6:48 ` [PATCH 07/21] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 08/21] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 10/21] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 11/21] iommu/mediatek: Add power-domain operation Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-13 7:03 ` Pi-Hsun Shih
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-14 9:33 ` Yong Wu
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-07-27 8:49 ` chao hao
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-08-07 2:13 ` Yong Wu
2020-07-11 6:48 ` [PATCH 12/21] iommu/mediatek: Add iova reserved function Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-13 7:33 ` Pi-Hsun Shih
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-14 9:32 ` Yong Wu
2020-07-11 6:48 ` [PATCH 13/21] iommu/mediatek: Make MTK_IOMMU depend on ARM64 Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 14/21] iommu/mediatek: Add single domain Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 15/21] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 16/21] iommu/mediatek: Support up to 34bit iova in tlb invalid Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu [this message]
2020-07-11 6:48 ` [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 18/21] iommu/mediatek: Add support for multi domain Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-23 20:47 ` Rob Herring
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-27 6:41 ` Yong Wu
2020-07-11 6:48 ` [PATCH 19/21] iommu/mediatek: Adjust the structure Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 20/21] iommu/mediatek: Add mt8192 support Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` [PATCH 21/21] memory: mtk-smi: " Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
2020-07-11 6:48 ` Yong Wu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200711064846.16007-18-yong.wu@mediatek.com \
--to=yong.wu@mediatek.com \
--cc=anan.sun@mediatek.com \
--cc=chao.hao@mediatek.com \
--cc=cui.zhang@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=evgreen@chromium.org \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=ming-fan.chen@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=srv_heupstream@mediatek.com \
--cc=tfiga@google.com \
--cc=will@kernel.org \
--cc=youlin.pei@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.