From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<chao.hao@mediatek.com>, <ming-fan.chen@mediatek.com>
Subject: [PATCH v2 22/23] iommu/mediatek: Add mt8192 support
Date: Sat, 5 Sep 2020 16:09:19 +0800 [thread overview]
Message-ID: <20200905080920.13396-23-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200905080920.13396-1-yong.wu@mediatek.com>
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff00000, size is 0x100000, then the end_address is 0xfff00000 +
0x100000 = 0x1 0000 0000. but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d0593d317240..ebc3767b62ab 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -171,6 +171,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
{.iova_base = 0, .size = SZ_4G},
};
+static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
+ { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
+ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_1M}, /* vdec: 4G ~ 8G gap: 1M */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_1M}, /* CAM/MDP: 8G ~ 12G */
+ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
+ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
+ #endif
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -967,11 +977,23 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
+static const struct mtk_iommu_plat_data mt8192_data = {
+ .m4u_plat = M4U_MT8192,
+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+ {0, 14, 16}, {0, 13, 18, 17}},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
+ { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5e346464cdf8..d2702eda25d4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ enum mtk_iommu_plat {
M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
+ M4U_MT8192,
};
struct mtk_iommu_iova_region;
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream@mediatek.com, chao.hao@mediatek.com,
linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com,
anan.sun@mediatek.com, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 22/23] iommu/mediatek: Add mt8192 support
Date: Sat, 5 Sep 2020 16:09:19 +0800 [thread overview]
Message-ID: <20200905080920.13396-23-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200905080920.13396-1-yong.wu@mediatek.com>
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff00000, size is 0x100000, then the end_address is 0xfff00000 +
0x100000 = 0x1 0000 0000. but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d0593d317240..ebc3767b62ab 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -171,6 +171,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
{.iova_base = 0, .size = SZ_4G},
};
+static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
+ { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
+ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_1M}, /* vdec: 4G ~ 8G gap: 1M */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_1M}, /* CAM/MDP: 8G ~ 12G */
+ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
+ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
+ #endif
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -967,11 +977,23 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
+static const struct mtk_iommu_plat_data mt8192_data = {
+ .m4u_plat = M4U_MT8192,
+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+ {0, 14, 16}, {0, 13, 18, 17}},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
+ { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5e346464cdf8..d2702eda25d4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ enum mtk_iommu_plat {
M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
+ M4U_MT8192,
};
struct mtk_iommu_iova_region;
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream@mediatek.com, chao.hao@mediatek.com,
linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 22/23] iommu/mediatek: Add mt8192 support
Date: Sat, 5 Sep 2020 16:09:19 +0800 [thread overview]
Message-ID: <20200905080920.13396-23-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200905080920.13396-1-yong.wu@mediatek.com>
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff00000, size is 0x100000, then the end_address is 0xfff00000 +
0x100000 = 0x1 0000 0000. but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d0593d317240..ebc3767b62ab 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -171,6 +171,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
{.iova_base = 0, .size = SZ_4G},
};
+static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
+ { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
+ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_1M}, /* vdec: 4G ~ 8G gap: 1M */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_1M}, /* CAM/MDP: 8G ~ 12G */
+ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
+ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
+ #endif
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -967,11 +977,23 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
+static const struct mtk_iommu_plat_data mt8192_data = {
+ .m4u_plat = M4U_MT8192,
+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+ {0, 14, 16}, {0, 13, 18, 17}},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
+ { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5e346464cdf8..d2702eda25d4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ enum mtk_iommu_plat {
M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
+ M4U_MT8192,
};
struct mtk_iommu_iova_region;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream@mediatek.com, chao.hao@mediatek.com,
linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 22/23] iommu/mediatek: Add mt8192 support
Date: Sat, 5 Sep 2020 16:09:19 +0800 [thread overview]
Message-ID: <20200905080920.13396-23-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200905080920.13396-1-yong.wu@mediatek.com>
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff00000, size is 0x100000, then the end_address is 0xfff00000 +
0x100000 = 0x1 0000 0000. but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d0593d317240..ebc3767b62ab 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -171,6 +171,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
{.iova_base = 0, .size = SZ_4G},
};
+static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
+ { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
+ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_1M}, /* vdec: 4G ~ 8G gap: 1M */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_1M}, /* CAM/MDP: 8G ~ 12G */
+ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
+ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
+ #endif
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -967,11 +977,23 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
+static const struct mtk_iommu_plat_data mt8192_data = {
+ .m4u_plat = M4U_MT8192,
+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+ {0, 14, 16}, {0, 13, 18, 17}},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
+ { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5e346464cdf8..d2702eda25d4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ enum mtk_iommu_plat {
M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
+ M4U_MT8192,
};
struct mtk_iommu_iova_region;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-05 8:14 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-05 8:08 [PATCH v2 00/23] MT8192 IOMMU support Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` [PATCH v2 01/23] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-14 23:22 ` Rob Herring
2020-09-14 23:22 ` Rob Herring
2020-09-14 23:22 ` Rob Herring
2020-09-14 23:22 ` Rob Herring
2020-09-15 5:49 ` Yong Wu
2020-09-15 5:49 ` Yong Wu
2020-09-15 5:49 ` Yong Wu
2020-09-15 5:49 ` Yong Wu
2020-09-18 16:07 ` Rob Herring
2020-09-18 16:07 ` Rob Herring
2020-09-18 16:07 ` Rob Herring
2020-09-18 16:07 ` Rob Herring
2020-09-05 8:08 ` [PATCH v2 02/23] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-05 8:08 ` Yong Wu
2020-09-14 23:23 ` Rob Herring
2020-09-14 23:23 ` Rob Herring
2020-09-14 23:23 ` Rob Herring
2020-09-14 23:23 ` Rob Herring
2020-09-15 5:55 ` Yong Wu
2020-09-15 5:55 ` Yong Wu
2020-09-15 5:55 ` Yong Wu
2020-09-15 5:55 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 03/23] dt-bindings: memory: mediatek: Add a common larb-port header file Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 04/23] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 05/23] dt-bindings: memory: mediatek: Add domain definition Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 06/23] dt-bindings: mediatek: Add binding for mt8192 IOMMU and SMI Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-15 0:42 ` Rob Herring
2020-09-15 0:42 ` Rob Herring
2020-09-15 0:42 ` Rob Herring
2020-09-15 0:42 ` Rob Herring
2020-09-05 8:09 ` [PATCH v2 07/23] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 08/23] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 09/23] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 10/23] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 11/23] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 12/23] iommu/mediatek: Move hw_init into attach_device Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 13/23] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 14/23] iommu/mediatek: Add power-domain operation Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 15/23] iommu/mediatek: Add iova reserved function Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 16/23] iommu/mediatek: Add single domain Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 17/23] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 18/23] iommu/mediatek: Support up to 34bit iova in tlb flush Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 19/23] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 20/23] iommu/mediatek: Add support for multi domain Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 21/23] iommu/mediatek: Adjust the structure Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu [this message]
2020-09-05 8:09 ` [PATCH v2 22/23] iommu/mediatek: Add mt8192 support Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` [PATCH v2 23/23] memory: mtk-smi: " Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
2020-09-05 8:09 ` Yong Wu
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