Re: [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management

From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management
Date: Mon, 26 Oct 2020 09:50:17 +0800	[thread overview]
Message-ID: <202010260937.3RIfH3Ep-lkp@intel.com> (raw)
In-Reply-To: <20201025221735.3062-45-digetx@gmail.com>

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Hi Dmitry,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.10-rc1 next-20201023]
[cannot apply to tegra/for-next robh/for-next tegra-drm/drm/tegra/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/Introduce-memory-interconnect-for-NVIDIA-Tegra-SoCs/20201026-062401
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3650b228f83adda7e5ee532e2b90429c03f7b9ec
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/7ceea541a585d7d6be0fa35c90a735f69820005f
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dmitry-Osipenko/Introduce-memory-interconnect-for-NVIDIA-Tegra-SoCs/20201026-062401
        git checkout 7ceea541a585d7d6be0fa35c90a735f69820005f
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/tegra/plane.c: In function 'tegra_plane_check_memory_bandwidth':
>> drivers/gpu/drm/tegra/plane.c:221:41: warning: variable 'dst_h' set but not used [-Wunused-but-set-variable]
     221 |  unsigned int i, bpp, bpp_plane, dst_w, dst_h, src_w, src_h, mul;
         |                                         ^~~~~

vim +/dst_h +221 drivers/gpu/drm/tegra/plane.c

   217	
   218	static int tegra_plane_check_memory_bandwidth(struct drm_plane_state *state)
   219	{
   220		struct tegra_plane_state *tegra_state = to_tegra_plane_state(state);
 > 221		unsigned int i, bpp, bpp_plane, dst_w, dst_h, src_w, src_h, mul;
   222		u32 avg_bandwidth = 0, peak_bandwidth;
   223		const struct tegra_dc_soc_info *soc;
   224		const struct drm_format_info *fmt;
   225		struct drm_crtc_state *crtc_state;
   226	
   227		if (!state->visible)
   228			return 0;
   229	
   230		crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
   231		if (!crtc_state)
   232			return -EINVAL;
   233	
   234		src_w = drm_rect_width(&state->src) >> 16;
   235		src_h = drm_rect_height(&state->src) >> 16;
   236		dst_w = drm_rect_width(&state->dst);
   237		dst_h = drm_rect_height(&state->dst);
   238	
   239		fmt = state->fb->format;
   240		soc = to_tegra_dc(state->crtc)->soc;
   241	
   242		/*
   243		 * Note that real memory bandwidth vary depending on format and
   244		 * memory layout, we are not taking that into account because small
   245		 * estimation error isn't important since bandwidth is rounded up
   246		 * anyway.
   247		 */
   248		for (i = 0, bpp = 0; i < fmt->num_planes; i++) {
   249			bpp_plane = fmt->cpp[i] * 8;
   250	
   251			/*
   252			 * Sub-sampling is relevant for chroma planes only and vertical
   253			 * readouts are not cached, hence only horizontal sub-sampling
   254			 * matters.
   255			 */
   256			if (i > 0)
   257				bpp_plane /= fmt->hsub;
   258	
   259			bpp += bpp_plane;
   260		}
   261	
   262		/*
   263		 * Horizontal downscale takes extra bandwidth which roughly depends
   264		 * on the scaled width.
   265		 */
   266		if (src_w > dst_w)
   267			mul = (src_w - dst_w) * bpp / 2048 + 1;
   268		else
   269			mul = 1;
   270	
   271		/* average bandwidth in bytes/s */
   272		avg_bandwidth  = src_w * src_h * bpp / 8 * mul;
   273		avg_bandwidth *= drm_mode_vrefresh(&crtc_state->mode);
   274	
   275		/* mode.clock in kHz, peak bandwidth in kbit/s */
   276		peak_bandwidth = crtc_state->mode.clock * bpp * mul;
   277	
   278		/* ICC bandwidth in kbyte/s */
   279		peak_bandwidth = kbps_to_icc(peak_bandwidth);
   280		avg_bandwidth  = Bps_to_icc(avg_bandwidth);
   281	
   282		/*
   283		 * Tegra30/114 Memory Controller can't interleave DC memory requests
   284		 * and DC uses 16-bytes atom for the tiled windows, while DDR3 uses 32
   285		 * bytes atom. Hence there is x2 memory overfetch for tiled framebuffer
   286		 * and DDR3 on older SoCs.
   287		 */
   288		if (soc->plane_tiled_memory_bandwidth_x2 &&
   289		    tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) {
   290			peak_bandwidth *= 2;
   291			avg_bandwidth *= 2;
   292		}
   293	
   294		tegra_state->peak_memory_bandwidth = peak_bandwidth;
   295		tegra_state->avg_memory_bandwidth = avg_bandwidth;
   296	
   297		return 0;
   298	}
   299	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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