From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v6 39/52] memory: tegra30: Support interconnect framework Date: Mon, 26 Oct 2020 01:17:22 +0300 [thread overview] Message-ID: <20201025221735.3062-40-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra30-emc.c | 184 ++++++++++++++++++++++++++++- drivers/memory/tegra/tegra30.c | 119 +++++++++++++++++++ 3 files changed, 302 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 61cdb5c04b18..73a5c5bca480 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -23,6 +23,7 @@ config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra30 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 78f770cf0d64..66eae944ca6d 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,6 +14,7 @@ #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/err.h> +#include <linux/interconnect-provider.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> @@ -21,6 +22,8 @@ #include <linux/module.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/slab.h> #include <linux/sort.h> #include <linux/types.h> @@ -326,6 +329,8 @@ struct emc_timing { struct tegra_emc { struct device *dev; struct tegra_mc *mc; + struct opp_table *opp_table; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; @@ -973,11 +978,12 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc, return err; dev_info(emc->dev, - "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", + "got %u timings for RAM code %u (min %luMHz max %luMHz) OPP HW ver. 0x%lx\n", emc->num_timings, tegra_read_ram_code(), emc->timings[0].rate / 1000000, - emc->timings[emc->num_timings - 1].rate / 1000000); + emc->timings[emc->num_timings - 1].rate / 1000000, + BIT(tegra_sku_info.soc_speedo_id)); return 0; } @@ -1264,6 +1270,172 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + long rounded_rate; + int err; + + /* + * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sample on both EMC clock edges. + */ + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + rounded_rate = emc_round_rate(rate, 0, U32_MAX, emc); + if (rounded_rate < 0) + return rounded_rate; + + err = dev_pm_opp_set_rate(emc->dev, rounded_rate); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc = emc->mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, "OPP table not found\n"); + dev_err(emc->dev, "please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + emc->opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + emc->opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(emc->opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(emc->opp_table), + "failed to prepare OPP table\n"); + + opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(emc->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + return 0; + +put_hw: + dev_pm_opp_put_supported_hw(emc->opp_table); +put_table: + dev_pm_opp_put_opp_table(emc->opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1329,8 +1501,13 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -1341,6 +1518,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1398,6 +1577,7 @@ static struct platform_driver tegra_emc_driver = { .of_match_table = tegra_emc_of_match, .pm = &tegra_emc_pm_ops, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 05780a0c6d39..f4ff967d7a10 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1083,6 +1083,124 @@ static const struct tegra_mc_reset tegra30_mc_resets[] = { TEGRA30_MC_RESET(VI, 0x200, 0x204, 17), }; +static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, + const struct tegra_mc_client *client, + unsigned int bandwidth_mbytes_sec) +{ + u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div; + const struct tegra_mc_la *la = &client->la; + unsigned int fifo_size = client->fifo_size; + u32 arb_nsec, la_ticks, value; + + /* see 18.4.1 Client Configuration in Tegra3 TRM v03p */ + if (bandwidth_mbytes_sec) + arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec; + else + arb_nsec = U32_MAX; + + /* + * Latency allowness should be set with consideration for the module's + * latency tolerance and internal buffering capabilities. + * + * Display memory clients use isochronous transfers and have very low + * tolerance to a belated transfers. Hence we need to compensate the + * memory arbitration imperfection for them in order to prevent FIFO + * underflow condition when memory bus is busy. + * + * VI clients also need a stronger compensation. + */ + switch (client->swgroup) { + case TEGRA_SWGROUP_MPCORE: + /* we always want lower latency for CPU, hence don't touch it */ + return; + + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 2; + break; + + case TEGRA_SWGROUP_VI: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 1; + break; + + default: + arb_tolerance_compensation_nsec = 150; + arb_tolerance_compensation_div = 1; + break; + } + + if (arb_nsec > arb_tolerance_compensation_nsec) + arb_nsec -= arb_tolerance_compensation_nsec; + else + arb_nsec = 0; + + arb_nsec /= arb_tolerance_compensation_div; + + /* + * Latency allowance is a number of ticks a request from a particular + * client may wait in the EMEM arbiter before it becomes a high-priority + * request. + */ + la_ticks = arb_nsec / mc->tick; + la_ticks = min(la_ticks, la->mask); + + value = mc_readl(mc, la->reg); + value &= ~(la->mask << la->shift); + value |= la_ticks << la->shift; + mc_writel(mc, value, la->reg); +} + +static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct icc_provider *provider = src->provider; + struct tegra_mc *mc = container_of(provider, struct tegra_mc, provider); + const struct tegra_mc_client *client = &mc->soc->clients[src->id]; + u64 peak_bandwidth = icc_units_to_bps(src->peak_bw); + + /* + * Skip pre-initialization that is done by icc_node_add(), which sets + * bandwidth to maximum for all clients before drivers are loaded. + * + * This doesn't make sense for us because we don't have drivers for all + * clients and it's okay to keep configuration left from bootloader + * during boot, at least for today. + */ + if (src == dst) + return 0; + + /* convert bytes/sec to megabytes/sec */ + do_div(peak_bandwidth, 1000000); + + tegra30_mc_tune_client_latency(mc, client, peak_bandwidth); + + return 0; +} + +static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could high bandwidth pressure during initial fulling-up + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag == TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = { + .aggregate = tegra30_mc_icc_aggreate, + .set = tegra30_mc_icc_set, +}; + const struct tegra_mc_soc tegra30_mc_soc = { .clients = tegra30_mc_clients, .num_clients = ARRAY_SIZE(tegra30_mc_clients), @@ -1097,4 +1215,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra30_mc_resets, .num_resets = ARRAY_SIZE(tegra30_mc_resets), + .icc_ops = &tegra30_mc_icc_ops, }; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v6 39/52] memory: tegra30: Support interconnect framework Date: Mon, 26 Oct 2020 01:17:22 +0300 [thread overview] Message-ID: <20201025221735.3062-40-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra30-emc.c | 184 ++++++++++++++++++++++++++++- drivers/memory/tegra/tegra30.c | 119 +++++++++++++++++++ 3 files changed, 302 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 61cdb5c04b18..73a5c5bca480 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -23,6 +23,7 @@ config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra30 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 78f770cf0d64..66eae944ca6d 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,6 +14,7 @@ #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/err.h> +#include <linux/interconnect-provider.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> @@ -21,6 +22,8 @@ #include <linux/module.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/slab.h> #include <linux/sort.h> #include <linux/types.h> @@ -326,6 +329,8 @@ struct emc_timing { struct tegra_emc { struct device *dev; struct tegra_mc *mc; + struct opp_table *opp_table; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; @@ -973,11 +978,12 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc, return err; dev_info(emc->dev, - "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", + "got %u timings for RAM code %u (min %luMHz max %luMHz) OPP HW ver. 0x%lx\n", emc->num_timings, tegra_read_ram_code(), emc->timings[0].rate / 1000000, - emc->timings[emc->num_timings - 1].rate / 1000000); + emc->timings[emc->num_timings - 1].rate / 1000000, + BIT(tegra_sku_info.soc_speedo_id)); return 0; } @@ -1264,6 +1270,172 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + long rounded_rate; + int err; + + /* + * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sample on both EMC clock edges. + */ + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + rounded_rate = emc_round_rate(rate, 0, U32_MAX, emc); + if (rounded_rate < 0) + return rounded_rate; + + err = dev_pm_opp_set_rate(emc->dev, rounded_rate); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc = emc->mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, "OPP table not found\n"); + dev_err(emc->dev, "please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + emc->opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + emc->opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(emc->opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(emc->opp_table), + "failed to prepare OPP table\n"); + + opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(emc->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + return 0; + +put_hw: + dev_pm_opp_put_supported_hw(emc->opp_table); +put_table: + dev_pm_opp_put_opp_table(emc->opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1329,8 +1501,13 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -1341,6 +1518,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1398,6 +1577,7 @@ static struct platform_driver tegra_emc_driver = { .of_match_table = tegra_emc_of_match, .pm = &tegra_emc_pm_ops, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 05780a0c6d39..f4ff967d7a10 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1083,6 +1083,124 @@ static const struct tegra_mc_reset tegra30_mc_resets[] = { TEGRA30_MC_RESET(VI, 0x200, 0x204, 17), }; +static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, + const struct tegra_mc_client *client, + unsigned int bandwidth_mbytes_sec) +{ + u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div; + const struct tegra_mc_la *la = &client->la; + unsigned int fifo_size = client->fifo_size; + u32 arb_nsec, la_ticks, value; + + /* see 18.4.1 Client Configuration in Tegra3 TRM v03p */ + if (bandwidth_mbytes_sec) + arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec; + else + arb_nsec = U32_MAX; + + /* + * Latency allowness should be set with consideration for the module's + * latency tolerance and internal buffering capabilities. + * + * Display memory clients use isochronous transfers and have very low + * tolerance to a belated transfers. Hence we need to compensate the + * memory arbitration imperfection for them in order to prevent FIFO + * underflow condition when memory bus is busy. + * + * VI clients also need a stronger compensation. + */ + switch (client->swgroup) { + case TEGRA_SWGROUP_MPCORE: + /* we always want lower latency for CPU, hence don't touch it */ + return; + + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 2; + break; + + case TEGRA_SWGROUP_VI: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 1; + break; + + default: + arb_tolerance_compensation_nsec = 150; + arb_tolerance_compensation_div = 1; + break; + } + + if (arb_nsec > arb_tolerance_compensation_nsec) + arb_nsec -= arb_tolerance_compensation_nsec; + else + arb_nsec = 0; + + arb_nsec /= arb_tolerance_compensation_div; + + /* + * Latency allowance is a number of ticks a request from a particular + * client may wait in the EMEM arbiter before it becomes a high-priority + * request. + */ + la_ticks = arb_nsec / mc->tick; + la_ticks = min(la_ticks, la->mask); + + value = mc_readl(mc, la->reg); + value &= ~(la->mask << la->shift); + value |= la_ticks << la->shift; + mc_writel(mc, value, la->reg); +} + +static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct icc_provider *provider = src->provider; + struct tegra_mc *mc = container_of(provider, struct tegra_mc, provider); + const struct tegra_mc_client *client = &mc->soc->clients[src->id]; + u64 peak_bandwidth = icc_units_to_bps(src->peak_bw); + + /* + * Skip pre-initialization that is done by icc_node_add(), which sets + * bandwidth to maximum for all clients before drivers are loaded. + * + * This doesn't make sense for us because we don't have drivers for all + * clients and it's okay to keep configuration left from bootloader + * during boot, at least for today. + */ + if (src == dst) + return 0; + + /* convert bytes/sec to megabytes/sec */ + do_div(peak_bandwidth, 1000000); + + tegra30_mc_tune_client_latency(mc, client, peak_bandwidth); + + return 0; +} + +static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could high bandwidth pressure during initial fulling-up + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag == TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = { + .aggregate = tegra30_mc_icc_aggreate, + .set = tegra30_mc_icc_set, +}; + const struct tegra_mc_soc tegra30_mc_soc = { .clients = tegra30_mc_clients, .num_clients = ARRAY_SIZE(tegra30_mc_clients), @@ -1097,4 +1215,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra30_mc_resets, .num_resets = ARRAY_SIZE(tegra30_mc_resets), + .icc_ops = &tegra30_mc_icc_ops, }; -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-25 22:20 UTC|newest] Thread overview: 290+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-25 22:16 [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 01/52] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:04 ` Thierry Reding 2020-10-27 13:04 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 02/52] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:17 ` Thierry Reding 2020-10-27 13:17 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 03/52] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:18 ` Thierry Reding 2020-10-27 13:18 ` Thierry Reding 2020-10-28 15:16 ` Rob Herring 2020-10-28 15:16 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Dmitry Osipenko 2020-10-27 8:54 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Krzysztof Kozlowski 2020-10-27 8:54 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:23 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 06/52] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 07/52] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 08/52] dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-28 15:26 ` Rob Herring 2020-10-28 15:26 ` Rob Herring 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-27 13:22 ` Thierry Reding 2020-10-27 13:22 ` Thierry Reding 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-28 15:28 ` Rob Herring 2020-10-28 15:28 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 10/52] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 11/52] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:29 ` Rob Herring 2020-10-28 15:29 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:49 ` Rob Herring 2020-10-26 12:49 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 13/52] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:51 ` Rob Herring 2020-10-26 12:51 ` Rob Herring 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 14/52] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 15/52] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 16/52] dt-bindings: host1x: Document new " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 17/52] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 18/52] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 19/52] dt-bindings: memory: tegra124: " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-28 15:31 ` Rob Herring 2020-10-28 15:31 ` Rob Herring 2020-10-25 22:17 ` [PATCH v6 20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 21/52] ARM: tegra: Add interconnect properties to " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 13:30 ` Thierry Reding 2020-10-27 13:30 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 23/52] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 26/52] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 27/52] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 28/52] memory: tegra: Add and use devm_tegra_get_memory_controller() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 13:35 ` Thierry Reding 2020-10-27 13:35 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 29/52] memory: tegra-mc: Add interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:48 ` Thierry Reding 2020-10-27 13:48 ` Thierry Reding 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 30/52] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:49 ` Thierry Reding 2020-10-27 13:49 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 31/52] memory: tegra20-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 32/52] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:52 ` Thierry Reding 2020-10-27 13:52 ` Thierry Reding 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 33/52] memory: tegra20: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 14:11 ` Thierry Reding 2020-10-27 14:11 ` Thierry Reding 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 34/52] memory: tegra20-emc: Don't parse emc-stats node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 35/52] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 36/52] memory: tegra: Add FIFO sizes to Tegra30 memory clients Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 37/52] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 38/52] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko [this message] 2020-10-25 22:17 ` [PATCH v6 39/52] memory: tegra30: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 4:04 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 41/52] memory: tegra124-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 42/52] memory: tegra124: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 43/52] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 1:50 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 45/52] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 46/52] opp: Put interconnect paths outside of opp_table_lock Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-28 4:03 ` Viresh Kumar 2020-10-28 4:03 ` Viresh Kumar 2020-10-25 22:17 ` [PATCH v6 47/52] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:16 ` Chanwoo Choi 2020-10-26 3:16 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 48/52] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:18 ` Chanwoo Choi 2020-10-26 3:18 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 49/52] PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-03 2:22 ` Chanwoo Choi 2020-11-03 2:22 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 50/52] PM / devfreq: tegra30: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:17 ` Chanwoo Choi 2020-10-26 3:17 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 51/52] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 2:50 ` kernel test robot 2020-10-26 3:45 ` kernel test robot 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:57 ` Chanwoo Choi 2020-11-01 15:57 ` Chanwoo Choi 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:45 ` Chanwoo Choi 2020-11-01 15:45 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 52/52] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 15:20 ` Chanwoo Choi 2020-11-01 15:20 ` Chanwoo Choi 2020-10-26 15:08 ` [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Krzysztof Kozlowski 2020-10-26 15:08 ` Krzysztof Kozlowski 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 20:31 ` Dmitry Osipenko 2020-10-27 20:31 ` Dmitry Osipenko
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