From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v6 18/52] dt-bindings: memory: tegra30: Add memory client IDs Date: Mon, 26 Oct 2020 01:17:01 +0300 [thread overview] Message-ID: <20201025221735.3062-19-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v6 18/52] dt-bindings: memory: tegra30: Add memory client IDs Date: Mon, 26 Oct 2020 01:17:01 +0300 [thread overview] Message-ID: <20201025221735.3062-19-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-25 22:21 UTC|newest] Thread overview: 290+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-25 22:16 [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 01/52] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:04 ` Thierry Reding 2020-10-27 13:04 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 02/52] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:17 ` Thierry Reding 2020-10-27 13:17 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 03/52] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:18 ` Thierry Reding 2020-10-27 13:18 ` Thierry Reding 2020-10-28 15:16 ` Rob Herring 2020-10-28 15:16 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Dmitry Osipenko 2020-10-27 8:54 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Krzysztof Kozlowski 2020-10-27 8:54 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:23 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 06/52] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 07/52] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 08/52] dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-28 15:26 ` Rob Herring 2020-10-28 15:26 ` Rob Herring 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-27 13:22 ` Thierry Reding 2020-10-27 13:22 ` Thierry Reding 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-28 15:28 ` Rob Herring 2020-10-28 15:28 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 10/52] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 11/52] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:29 ` Rob Herring 2020-10-28 15:29 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:49 ` Rob Herring 2020-10-26 12:49 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 13/52] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:51 ` Rob Herring 2020-10-26 12:51 ` Rob Herring 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 14/52] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 15/52] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 16/52] dt-bindings: host1x: Document new " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 17/52] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko [this message] 2020-10-25 22:17 ` [PATCH v6 18/52] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 19/52] dt-bindings: memory: tegra124: " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-28 15:31 ` Rob Herring 2020-10-28 15:31 ` Rob Herring 2020-10-25 22:17 ` [PATCH v6 20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 21/52] ARM: tegra: Add interconnect properties to " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 13:30 ` Thierry Reding 2020-10-27 13:30 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 23/52] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 26/52] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 27/52] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 28/52] memory: tegra: Add and use devm_tegra_get_memory_controller() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 13:35 ` Thierry Reding 2020-10-27 13:35 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 29/52] memory: tegra-mc: Add interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:48 ` Thierry Reding 2020-10-27 13:48 ` Thierry Reding 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 30/52] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:49 ` Thierry Reding 2020-10-27 13:49 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 31/52] memory: tegra20-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 32/52] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:52 ` Thierry Reding 2020-10-27 13:52 ` Thierry Reding 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 33/52] memory: tegra20: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 14:11 ` Thierry Reding 2020-10-27 14:11 ` Thierry Reding 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 34/52] memory: tegra20-emc: Don't parse emc-stats node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 35/52] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 36/52] memory: tegra: Add FIFO sizes to Tegra30 memory clients Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 37/52] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 38/52] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 39/52] memory: tegra30: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 4:04 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 41/52] memory: tegra124-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 42/52] memory: tegra124: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 43/52] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 1:50 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 45/52] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 46/52] opp: Put interconnect paths outside of opp_table_lock Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-28 4:03 ` Viresh Kumar 2020-10-28 4:03 ` Viresh Kumar 2020-10-25 22:17 ` [PATCH v6 47/52] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:16 ` Chanwoo Choi 2020-10-26 3:16 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 48/52] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:18 ` Chanwoo Choi 2020-10-26 3:18 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 49/52] PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-03 2:22 ` Chanwoo Choi 2020-11-03 2:22 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 50/52] PM / devfreq: tegra30: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:17 ` Chanwoo Choi 2020-10-26 3:17 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 51/52] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 2:50 ` kernel test robot 2020-10-26 3:45 ` kernel test robot 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:57 ` Chanwoo Choi 2020-11-01 15:57 ` Chanwoo Choi 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:45 ` Chanwoo Choi 2020-11-01 15:45 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 52/52] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 15:20 ` Chanwoo Choi 2020-11-01 15:20 ` Chanwoo Choi 2020-10-26 15:08 ` [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Krzysztof Kozlowski 2020-10-26 15:08 ` Krzysztof Kozlowski 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 20:31 ` Dmitry Osipenko 2020-10-27 20:31 ` Dmitry Osipenko
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