From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Date: Mon, 26 Oct 2020 01:17:23 +0300 [thread overview] Message-ID: <20201025221735.3062-41-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> This patch adds modularization support to the Tegra124 EMC driver. Driver now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module, hence this patch adds prepare/complete callbacks, similar to what is done for Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/Makefile | 2 +- drivers/clk/tegra/clk-tegra124-emc.c | 41 ++++++++++++++++++++++++---- drivers/clk/tegra/clk-tegra124.c | 27 ++++++++++++++++-- drivers/clk/tegra/clk.h | 16 +++-------- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra124-emc.c | 31 ++++++++++++++------- include/linux/clk/tegra.h | 9 ++++++ include/soc/tegra/emc.h | 16 ----------- 8 files changed, 96 insertions(+), 48 deletions(-) delete mode 100644 include/soc/tegra/emc.h diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index eec2313fd37e..c3f6549be069 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o -obj-$(CONFIG_TEGRA124_EMC) += clk-tegra124-emc.o +obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index 745f9faa98d8..bdf6f4a51617 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -11,7 +11,9 @@ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/clk/tegra.h> #include <linux/delay.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_address.h> @@ -21,7 +23,6 @@ #include <linux/string.h> #include <soc/tegra/fuse.h> -#include <soc/tegra/emc.h> #include "clk.h" @@ -80,6 +81,9 @@ struct tegra_clk_emc { int num_timings; struct emc_timing *timings; spinlock_t *lock; + + tegra124_emc_prepare_timing_change_cb *prepare_timing_change; + tegra124_emc_complete_timing_change_cb *complete_timing_change; }; /* Common clock framework callback implementations */ @@ -176,6 +180,9 @@ static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) if (tegra->emc) return tegra->emc; + if (!tegra->prepare_timing_change || !tegra->complete_timing_change) + return NULL; + if (!tegra->emc_node) return NULL; @@ -241,7 +248,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; - err = tegra_emc_prepare_timing_change(emc, timing->rate); + err = tegra->prepare_timing_change(emc, timing->rate); if (err) return err; @@ -259,7 +266,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, spin_unlock_irqrestore(tegra->lock, flags); - tegra_emc_complete_timing_change(emc, timing->rate); + tegra->complete_timing_change(emc, timing->rate); clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); clk_disable_unprepare(tegra->prev_parent); @@ -473,8 +480,8 @@ static const struct clk_ops tegra_clk_emc_ops = { .get_parent = emc_get_parent, }; -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock) +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock) { struct tegra_clk_emc *tegra; struct clk_init_data init; @@ -538,3 +545,27 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, return clk; }; + +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ + struct clk *clk = __clk_lookup("emc"); + struct tegra_clk_emc *tegra; + struct clk_hw *hw; + + if (clk) { + hw = __clk_get_hw(clk); + tegra = container_of(hw, struct tegra_clk_emc, hw); + + tegra->prepare_timing_change = prep_cb; + tegra->complete_timing_change = complete_cb; + } +} +EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks); + +bool tegra124_clk_emc_driver_available(struct clk_hw *hw) +{ + struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); + + return tegra->prepare_timing_change && tegra->complete_timing_change; +} diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e931319dcc9d..b4f2ae4066a6 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -929,6 +929,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = false }, }; static struct tegra_devclk devclks[] __initdata = { @@ -1500,6 +1501,26 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) writel(plld_base, clk_base + PLLD_BASE); } +static struct clk *tegra124_clk_src_onecell_get(struct of_phandle_args *clkspec, + void *data) +{ + struct clk_hw *hw; + struct clk *clk; + + clk = of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + hw = __clk_get_hw(clk); + + if (clkspec->args[0] == TEGRA124_CLK_EMC) { + if (!tegra124_clk_emc_driver_available(hw)) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + /** * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 * @np: struct device_node * of the DT node for the SoC CAR IP block @@ -1516,10 +1537,10 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) &pll_x_params); tegra_init_special_resets(1, tegra124_reset_assert, tegra124_reset_deassert); - tegra_add_of_provider(np, of_clk_src_onecell_get); + tegra_add_of_provider(np, tegra124_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, - &emc_lock); + clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np, + &emc_lock); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 6b565f6b5f66..2da7c93c1a6c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -881,18 +881,6 @@ void tegra_super_clk_gen5_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); -#ifdef CONFIG_TEGRA124_EMC -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock); -#else -static inline struct clk *tegra_clk_register_emc(void __iomem *base, - struct device_node *np, - spinlock_t *lock) -{ - return NULL; -} -#endif - void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void); void tegra114_clock_tune_cpu_trimmers_init(void); @@ -922,6 +910,10 @@ void tegra_clk_periph_resume(void); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw); struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter); +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock); +bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw); + struct clk *tegra210_clk_register_emc(struct device_node *np, void __iomem *regs); diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 73a5c5bca480..94536dc4c495 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -31,7 +31,7 @@ config TEGRA30_EMC external memory. config TEGRA124_EMC - bool "NVIDIA Tegra124 External Memory Controller driver" + tristate "NVIDIA Tegra124 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_124_SOC help diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index b92259d4fbd1..48e772ec544d 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -9,16 +9,17 @@ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/clk/tegra.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/sort.h> #include <linux/string.h> -#include <soc/tegra/emc.h> #include <soc/tegra/fuse.h> #include <soc/tegra/mc.h> @@ -562,8 +563,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, return timing; } -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate) +static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -790,8 +791,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc, return 0; } -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate) +static void tegra_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -987,6 +988,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra132-emc" }, {} }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct device_node * tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) @@ -1228,9 +1230,19 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); + tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change, + tegra_emc_complete_timing_change); + if (IS_ENABLED(CONFIG_DEBUG_FS)) emc_debugfs_init(&pdev->dev, emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; }; @@ -1242,9 +1254,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); +MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 3f01d43f0598..d4c5e607ef29 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -136,6 +136,8 @@ extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); extern void tegra210_clk_emc_update_setting(u32 emc_src_value); struct clk; +struct device_node; +struct tegra_emc; typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, @@ -146,6 +148,13 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb); + struct tegra210_clk_emc_config { unsigned long rate; bool same_freq; diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h deleted file mode 100644 index 05199a97ccf4..000000000000 --- a/include/soc/tegra/emc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 NVIDIA Corporation. All rights reserved. - */ - -#ifndef __SOC_TEGRA_EMC_H__ -#define __SOC_TEGRA_EMC_H__ - -struct tegra_emc; - -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate); -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate); - -#endif /* __SOC_TEGRA_EMC_H__ */ -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Date: Mon, 26 Oct 2020 01:17:23 +0300 [thread overview] Message-ID: <20201025221735.3062-41-digetx@gmail.com> (raw) In-Reply-To: <20201025221735.3062-1-digetx@gmail.com> This patch adds modularization support to the Tegra124 EMC driver. Driver now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module, hence this patch adds prepare/complete callbacks, similar to what is done for Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/Makefile | 2 +- drivers/clk/tegra/clk-tegra124-emc.c | 41 ++++++++++++++++++++++++---- drivers/clk/tegra/clk-tegra124.c | 27 ++++++++++++++++-- drivers/clk/tegra/clk.h | 16 +++-------- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra124-emc.c | 31 ++++++++++++++------- include/linux/clk/tegra.h | 9 ++++++ include/soc/tegra/emc.h | 16 ----------- 8 files changed, 96 insertions(+), 48 deletions(-) delete mode 100644 include/soc/tegra/emc.h diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index eec2313fd37e..c3f6549be069 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o -obj-$(CONFIG_TEGRA124_EMC) += clk-tegra124-emc.o +obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index 745f9faa98d8..bdf6f4a51617 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -11,7 +11,9 @@ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/clk/tegra.h> #include <linux/delay.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_address.h> @@ -21,7 +23,6 @@ #include <linux/string.h> #include <soc/tegra/fuse.h> -#include <soc/tegra/emc.h> #include "clk.h" @@ -80,6 +81,9 @@ struct tegra_clk_emc { int num_timings; struct emc_timing *timings; spinlock_t *lock; + + tegra124_emc_prepare_timing_change_cb *prepare_timing_change; + tegra124_emc_complete_timing_change_cb *complete_timing_change; }; /* Common clock framework callback implementations */ @@ -176,6 +180,9 @@ static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) if (tegra->emc) return tegra->emc; + if (!tegra->prepare_timing_change || !tegra->complete_timing_change) + return NULL; + if (!tegra->emc_node) return NULL; @@ -241,7 +248,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; - err = tegra_emc_prepare_timing_change(emc, timing->rate); + err = tegra->prepare_timing_change(emc, timing->rate); if (err) return err; @@ -259,7 +266,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, spin_unlock_irqrestore(tegra->lock, flags); - tegra_emc_complete_timing_change(emc, timing->rate); + tegra->complete_timing_change(emc, timing->rate); clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); clk_disable_unprepare(tegra->prev_parent); @@ -473,8 +480,8 @@ static const struct clk_ops tegra_clk_emc_ops = { .get_parent = emc_get_parent, }; -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock) +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock) { struct tegra_clk_emc *tegra; struct clk_init_data init; @@ -538,3 +545,27 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, return clk; }; + +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ + struct clk *clk = __clk_lookup("emc"); + struct tegra_clk_emc *tegra; + struct clk_hw *hw; + + if (clk) { + hw = __clk_get_hw(clk); + tegra = container_of(hw, struct tegra_clk_emc, hw); + + tegra->prepare_timing_change = prep_cb; + tegra->complete_timing_change = complete_cb; + } +} +EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks); + +bool tegra124_clk_emc_driver_available(struct clk_hw *hw) +{ + struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); + + return tegra->prepare_timing_change && tegra->complete_timing_change; +} diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e931319dcc9d..b4f2ae4066a6 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -929,6 +929,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = false }, }; static struct tegra_devclk devclks[] __initdata = { @@ -1500,6 +1501,26 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) writel(plld_base, clk_base + PLLD_BASE); } +static struct clk *tegra124_clk_src_onecell_get(struct of_phandle_args *clkspec, + void *data) +{ + struct clk_hw *hw; + struct clk *clk; + + clk = of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + hw = __clk_get_hw(clk); + + if (clkspec->args[0] == TEGRA124_CLK_EMC) { + if (!tegra124_clk_emc_driver_available(hw)) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + /** * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 * @np: struct device_node * of the DT node for the SoC CAR IP block @@ -1516,10 +1537,10 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) &pll_x_params); tegra_init_special_resets(1, tegra124_reset_assert, tegra124_reset_deassert); - tegra_add_of_provider(np, of_clk_src_onecell_get); + tegra_add_of_provider(np, tegra124_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, - &emc_lock); + clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np, + &emc_lock); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 6b565f6b5f66..2da7c93c1a6c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -881,18 +881,6 @@ void tegra_super_clk_gen5_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); -#ifdef CONFIG_TEGRA124_EMC -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock); -#else -static inline struct clk *tegra_clk_register_emc(void __iomem *base, - struct device_node *np, - spinlock_t *lock) -{ - return NULL; -} -#endif - void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void); void tegra114_clock_tune_cpu_trimmers_init(void); @@ -922,6 +910,10 @@ void tegra_clk_periph_resume(void); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw); struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter); +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock); +bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw); + struct clk *tegra210_clk_register_emc(struct device_node *np, void __iomem *regs); diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 73a5c5bca480..94536dc4c495 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -31,7 +31,7 @@ config TEGRA30_EMC external memory. config TEGRA124_EMC - bool "NVIDIA Tegra124 External Memory Controller driver" + tristate "NVIDIA Tegra124 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_124_SOC help diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index b92259d4fbd1..48e772ec544d 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -9,16 +9,17 @@ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/clk/tegra.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/sort.h> #include <linux/string.h> -#include <soc/tegra/emc.h> #include <soc/tegra/fuse.h> #include <soc/tegra/mc.h> @@ -562,8 +563,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, return timing; } -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate) +static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -790,8 +791,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc, return 0; } -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate) +static void tegra_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -987,6 +988,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra132-emc" }, {} }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct device_node * tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) @@ -1228,9 +1230,19 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); + tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change, + tegra_emc_complete_timing_change); + if (IS_ENABLED(CONFIG_DEBUG_FS)) emc_debugfs_init(&pdev->dev, emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; }; @@ -1242,9 +1254,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); +MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 3f01d43f0598..d4c5e607ef29 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -136,6 +136,8 @@ extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); extern void tegra210_clk_emc_update_setting(u32 emc_src_value); struct clk; +struct device_node; +struct tegra_emc; typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, @@ -146,6 +148,13 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb); + struct tegra210_clk_emc_config { unsigned long rate; bool same_freq; diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h deleted file mode 100644 index 05199a97ccf4..000000000000 --- a/include/soc/tegra/emc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 NVIDIA Corporation. All rights reserved. - */ - -#ifndef __SOC_TEGRA_EMC_H__ -#define __SOC_TEGRA_EMC_H__ - -struct tegra_emc; - -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate); -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate); - -#endif /* __SOC_TEGRA_EMC_H__ */ -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-25 22:20 UTC|newest] Thread overview: 290+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-25 22:16 [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 01/52] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:04 ` Thierry Reding 2020-10-27 13:04 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 02/52] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:17 ` Thierry Reding 2020-10-27 13:17 ` Thierry Reding 2020-10-25 22:16 ` [PATCH v6 03/52] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 13:18 ` Thierry Reding 2020-10-27 13:18 ` Thierry Reding 2020-10-28 15:16 ` Rob Herring 2020-10-28 15:16 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Dmitry Osipenko 2020-10-27 8:54 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Krzysztof Kozlowski 2020-10-27 8:54 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 19:30 ` Krzysztof Kozlowski 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-27 20:37 ` Dmitry Osipenko 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:35 ` Krzysztof Kozlowski 2020-10-28 15:23 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Rob Herring 2020-10-28 15:23 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 8:55 ` Krzysztof Kozlowski 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:17 ` Dmitry Osipenko 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-27 19:34 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 06/52] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-27 9:03 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 07/52] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-27 8:57 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 08/52] dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 9:02 ` Krzysztof Kozlowski 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:22 ` Dmitry Osipenko 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 19:44 ` Krzysztof Kozlowski 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-27 20:18 ` Dmitry Osipenko 2020-10-28 15:26 ` Rob Herring 2020-10-28 15:26 ` Rob Herring 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-31 19:53 ` Dmitry Osipenko 2020-10-27 13:22 ` Thierry Reding 2020-10-27 13:22 ` Thierry Reding 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-28 15:28 ` Rob Herring 2020-10-28 15:28 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 9:05 ` Krzysztof Kozlowski 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:18 ` Dmitry Osipenko 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-27 19:39 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 10/52] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:16 ` [PATCH v6 11/52] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:29 ` Rob Herring 2020-10-28 15:29 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:49 ` Rob Herring 2020-10-26 12:49 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 13/52] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-26 12:51 ` Rob Herring 2020-10-26 12:51 ` Rob Herring 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 10:25 ` Krzysztof Kozlowski 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:19 ` Dmitry Osipenko 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 19:48 ` Krzysztof Kozlowski 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-27 20:16 ` Dmitry Osipenko 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-28 19:27 ` Krzysztof Kozlowski 2020-10-25 22:16 ` [PATCH v6 14/52] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 15/52] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-28 15:30 ` Rob Herring 2020-10-28 15:30 ` Rob Herring 2020-10-25 22:16 ` [PATCH v6 16/52] dt-bindings: host1x: Document new " Dmitry Osipenko 2020-10-25 22:16 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 17/52] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 18/52] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 19/52] dt-bindings: memory: tegra124: " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-28 15:31 ` Rob Herring 2020-10-28 15:31 ` Rob Herring 2020-10-25 22:17 ` [PATCH v6 20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 9:10 ` Krzysztof Kozlowski 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-27 20:43 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 21/52] ARM: tegra: Add interconnect properties to " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 9:12 ` Krzysztof Kozlowski 2020-10-27 13:30 ` Thierry Reding 2020-10-27 13:30 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 9:15 ` Krzysztof Kozlowski 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-27 19:23 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 23/52] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-27 9:16 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-27 9:18 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 26/52] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 27/52] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 28/52] memory: tegra: Add and use devm_tegra_get_memory_controller() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 9:42 ` Krzysztof Kozlowski 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 19:24 ` Dmitry Osipenko 2020-10-27 13:35 ` Thierry Reding 2020-10-27 13:35 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 29/52] memory: tegra-mc: Add interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:48 ` Thierry Reding 2020-10-27 13:48 ` Thierry Reding 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-27 19:30 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 30/52] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:49 ` Thierry Reding 2020-10-27 13:49 ` Thierry Reding 2020-10-25 22:17 ` [PATCH v6 31/52] memory: tegra20-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:50 ` Thierry Reding 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-27 13:57 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 32/52] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 13:52 ` Thierry Reding 2020-10-27 13:52 ` Thierry Reding 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-27 19:38 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 33/52] memory: tegra20: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 10:09 ` Krzysztof Kozlowski 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 20:25 ` Dmitry Osipenko 2020-10-27 14:11 ` Thierry Reding 2020-10-27 14:11 ` Thierry Reding 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 20:22 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-27 21:12 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 34/52] memory: tegra20-emc: Don't parse emc-stats node Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 35/52] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 36/52] memory: tegra: Add FIFO sizes to Tegra30 memory clients Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 37/52] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 38/52] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 39/52] memory: tegra30: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko [this message] 2020-10-25 22:17 ` [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Dmitry Osipenko 2020-10-26 4:04 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 41/52] memory: tegra124-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 10:27 ` Krzysztof Kozlowski 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-27 20:30 ` Dmitry Osipenko 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-28 19:28 ` Krzysztof Kozlowski 2020-10-25 22:17 ` [PATCH v6 42/52] memory: tegra124: Support interconnect framework Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 43/52] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 1:50 ` kernel test robot 2020-10-25 22:17 ` [PATCH v6 45/52] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-25 22:17 ` [PATCH v6 46/52] opp: Put interconnect paths outside of opp_table_lock Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 5:10 ` Viresh Kumar 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-27 20:26 ` Dmitry Osipenko 2020-10-28 4:03 ` Viresh Kumar 2020-10-28 4:03 ` Viresh Kumar 2020-10-25 22:17 ` [PATCH v6 47/52] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:16 ` Chanwoo Choi 2020-10-26 3:16 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 48/52] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:18 ` Chanwoo Choi 2020-10-26 3:18 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 49/52] PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 13:31 ` Chanwoo Choi 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-01 14:12 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-02 20:08 ` Dmitry Osipenko 2020-11-03 2:22 ` Chanwoo Choi 2020-11-03 2:22 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 50/52] PM / devfreq: tegra30: Silence deferred probe error Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 3:17 ` Chanwoo Choi 2020-10-26 3:17 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 51/52] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-10-26 2:50 ` kernel test robot 2020-10-26 3:45 ` kernel test robot 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 14:39 ` Chanwoo Choi 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:23 ` Dmitry Osipenko 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:44 ` Chanwoo Choi 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:49 ` Dmitry Osipenko 2020-11-01 15:57 ` Chanwoo Choi 2020-11-01 15:57 ` Chanwoo Choi 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 19:58 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-02 20:00 ` Dmitry Osipenko 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 14:44 ` Chanwoo Choi 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:24 ` Dmitry Osipenko 2020-11-01 15:45 ` Chanwoo Choi 2020-11-01 15:45 ` Chanwoo Choi 2020-10-25 22:17 ` [PATCH v6 52/52] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko 2020-10-25 22:17 ` Dmitry Osipenko 2020-11-01 15:20 ` Chanwoo Choi 2020-11-01 15:20 ` Chanwoo Choi 2020-10-26 15:08 ` [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Krzysztof Kozlowski 2020-10-26 15:08 ` Krzysztof Kozlowski 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-26 19:14 ` Dmitry Osipenko 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 8:52 ` Krzysztof Kozlowski 2020-10-27 20:31 ` Dmitry Osipenko 2020-10-27 20:31 ` Dmitry Osipenko
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