From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: Helen Koike <helen.koike@collabora.com>
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org,
linux-sunxi@googlegroups.com,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Yong Deng <yong.deng@magewell.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Hans Verkuil <hans.verkuil@cisco.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Hans Verkuil <hverkuil@xs4all.nl>,
kevin.lhopital@hotmail.com
Subject: Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Date: Wed, 4 Nov 2020 11:54:59 +0100 [thread overview]
Message-ID: <20201104105459.GF285779@aptenodytes> (raw)
In-Reply-To: <5df82a6c-daa3-8e47-b7a4-85da60b87dd2@collabora.com>
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Hi Helen and thanks for the review,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > former, to be used with MIPI CSI-2.
> >
> > This implementation is inspired by the Allwinner BSP implementation.
> >
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > ---
> > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++++++++++++++++++-
> > 1 file changed, 160 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > index 1fa761ba6cbb..8bcd4bb79f60 100644
> > --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > @@ -24,6 +24,14 @@
> > #define SUN6I_DPHY_TX_CTL_REG 0x04
> > #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
> >
> > +#define SUN6I_DPHY_RX_CTL_REG 0x08
> > +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
> > +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
> > +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
> > +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
> > +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
> > +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
> > +
> > #define SUN6I_DPHY_TX_TIME0_REG 0x10
> > #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24)
> > #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
> > @@ -44,12 +52,29 @@
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
> >
> > +#define SUN6I_DPHY_RX_TIME0_REG 0x30
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
> > +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
> > +
> > +#define SUN6I_DPHY_RX_TIME1_REG 0x34
> > +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
> > +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xfffff)
> > +
> > +#define SUN6I_DPHY_RX_TIME2_REG 0x38
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
> > +
> > +#define SUN6I_DPHY_RX_TIME3_REG 0x40
> > +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0xffff) << 16)
> > +
> > #define SUN6I_DPHY_ANA0_REG 0x4c
> > #define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
> > #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
> > #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
> > #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
> > #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
> > +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
> >
> > #define SUN6I_DPHY_ANA1_REG 0x50
> > #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
> > @@ -92,6 +117,8 @@ struct sun6i_dphy {
> >
> > struct phy *phy;
> > struct phy_configure_opts_mipi_dphy config;
> > +
> > + int submode;
> > };
> >
> > static int sun6i_dphy_init(struct phy *phy)
> > @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_MIPI_DPHY)
> > + return -EINVAL;
> > +
> > + dphy->submode = submode;
>
> Shouldn't you check if the submode is valid here?
Yes that's a good point, thanks!
> > +
> > + return 0;
> > +}
> > +
> > static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > @@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > return 0;
> > }
> >
> > -static int sun6i_dphy_power_on(struct phy *phy)
> > +static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> > {
> > - struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
> >
> > regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
> > @@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
> > +{
> > + /* Physical clock rate is actually half of symbol rate with DDR. */
> > + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
> > + unsigned long dphy_clk_rate;
> > + unsigned int rx_dly;
> > + unsigned int lprst_dly;
> > + u32 value;
> > +
> > + dphy_clk_rate = clk_get_rate(dphy->mod_clk);
> > + if (!dphy_clk_rate)
> > + return -1;
> > +
> > + /* Hardcoded timing parameters from the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
> > + SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
> > + SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
> > + SUN6I_DPHY_RX_TIME0_LP_RX(255));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 8));
> > +
> > + /*
> > + * The Allwinner BSP has an alternative formula for LP_RX_ULPS_WP:
> > + * lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
> > + * but does not use it and hardcodes 255 instead.
> > + */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
> > + SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
> > + SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
> > +
> > + /* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
> > + SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + lprst_dly = 4 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
> > + SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
> > +
> > + /* Analog parameters are hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> > + SUN6I_DPHY_ANA0_REG_PWS |
> > + SUN6I_DPHY_ANA0_REG_SLV(7) |
> > + SUN6I_DPHY_ANA0_REG_SFB(2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > + SUN6I_DPHY_ANA1_REG_SVTT(4));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
> > + SUN6I_DPHY_ANA4_REG_DMPLVC |
> > + SUN6I_DPHY_ANA4_REG_DMPLVD(1));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
> > + SUN6I_DPHY_ANA2_REG_ENIB);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
> > + SUN6I_DPHY_ANA3_EN_LDOR |
> > + SUN6I_DPHY_ANA3_EN_LDOC |
> > + SUN6I_DPHY_ANA3_EN_LDOD);
> > +
> > + /*
> > + * Delay comes from the Allwinner BSP, likely for internal regulator
> > + * ramp-up.
> > + */
> > + udelay(3);
> > +
> > + value = SUN6I_DPHY_RX_CTL_EN_DBC | SUN6I_DPHY_RX_CTL_RX_CLK_FORCE;
> > +
> > + /*
> > + * Rx data lane force-enable bits are used as regular RX enable by the
> > + * Allwinner BSP.
> > + */
> > + if (dphy->config.lanes >= 1)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D0_FORCE;
> > + if (dphy->config.lanes >= 2)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D1_FORCE;
> > + if (dphy->config.lanes >= 3)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D2_FORCE;
> > + if (dphy->config.lanes == 4)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D3_FORCE;
>
> I would replace this by a switch case with fallthrough to avoid too many comparisons
> to the same value.
Okay, why not!
Cheers,
Paul
> Regards,
> Helen
>
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> > + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> > + SUN6I_DPHY_GCTL_EN);
> > +
> > + return 0;
> > +}
> > +
> > +static int sun6i_dphy_power_on(struct phy *phy)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + switch (dphy->submode) {
> > + case PHY_MIPI_DPHY_SUBMODE_TX:
> > + return sun6i_dphy_tx_power_on(dphy);
> > + case PHY_MIPI_DPHY_SUBMODE_RX:
> > + return sun6i_dphy_rx_power_on(dphy);
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > static int sun6i_dphy_power_off(struct phy *phy)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> >
> > - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > - SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 0);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
> >
> > return 0;
> > }
> > @@ -234,6 +389,7 @@ static int sun6i_dphy_exit(struct phy *phy)
> >
> >
> > static const struct phy_ops sun6i_dphy_ops = {
> > + .set_mode = sun6i_dphy_set_mode,
> > .configure = sun6i_dphy_configure,
> > .power_on = sun6i_dphy_power_on,
> > .power_off = sun6i_dphy_power_off,
> >
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: Helen Koike <helen.koike@collabora.com>
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, Maxime Ripard <mripard@kernel.org>,
Chen-Yu Tsai <wens@csie.org>, Hans Verkuil <hverkuil@xs4all.nl>,
linux-sunxi@googlegroups.com, Rob Herring <robh+dt@kernel.org>,
Vinod Koul <vkoul@kernel.org>, Yong Deng <yong.deng@magewell.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Hans Verkuil <hans.verkuil@cisco.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
kevin.lhopital@hotmail.com, linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Date: Wed, 4 Nov 2020 11:54:59 +0100 [thread overview]
Message-ID: <20201104105459.GF285779@aptenodytes> (raw)
In-Reply-To: <5df82a6c-daa3-8e47-b7a4-85da60b87dd2@collabora.com>
[-- Attachment #1.1: Type: text/plain, Size: 9502 bytes --]
Hi Helen and thanks for the review,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > former, to be used with MIPI CSI-2.
> >
> > This implementation is inspired by the Allwinner BSP implementation.
> >
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > ---
> > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++++++++++++++++++-
> > 1 file changed, 160 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > index 1fa761ba6cbb..8bcd4bb79f60 100644
> > --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > @@ -24,6 +24,14 @@
> > #define SUN6I_DPHY_TX_CTL_REG 0x04
> > #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
> >
> > +#define SUN6I_DPHY_RX_CTL_REG 0x08
> > +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
> > +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
> > +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
> > +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
> > +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
> > +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
> > +
> > #define SUN6I_DPHY_TX_TIME0_REG 0x10
> > #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24)
> > #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
> > @@ -44,12 +52,29 @@
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
> >
> > +#define SUN6I_DPHY_RX_TIME0_REG 0x30
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
> > +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
> > +
> > +#define SUN6I_DPHY_RX_TIME1_REG 0x34
> > +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
> > +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xfffff)
> > +
> > +#define SUN6I_DPHY_RX_TIME2_REG 0x38
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
> > +
> > +#define SUN6I_DPHY_RX_TIME3_REG 0x40
> > +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0xffff) << 16)
> > +
> > #define SUN6I_DPHY_ANA0_REG 0x4c
> > #define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
> > #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
> > #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
> > #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
> > #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
> > +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
> >
> > #define SUN6I_DPHY_ANA1_REG 0x50
> > #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
> > @@ -92,6 +117,8 @@ struct sun6i_dphy {
> >
> > struct phy *phy;
> > struct phy_configure_opts_mipi_dphy config;
> > +
> > + int submode;
> > };
> >
> > static int sun6i_dphy_init(struct phy *phy)
> > @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_MIPI_DPHY)
> > + return -EINVAL;
> > +
> > + dphy->submode = submode;
>
> Shouldn't you check if the submode is valid here?
Yes that's a good point, thanks!
> > +
> > + return 0;
> > +}
> > +
> > static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > @@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > return 0;
> > }
> >
> > -static int sun6i_dphy_power_on(struct phy *phy)
> > +static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> > {
> > - struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
> >
> > regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
> > @@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
> > +{
> > + /* Physical clock rate is actually half of symbol rate with DDR. */
> > + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
> > + unsigned long dphy_clk_rate;
> > + unsigned int rx_dly;
> > + unsigned int lprst_dly;
> > + u32 value;
> > +
> > + dphy_clk_rate = clk_get_rate(dphy->mod_clk);
> > + if (!dphy_clk_rate)
> > + return -1;
> > +
> > + /* Hardcoded timing parameters from the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
> > + SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
> > + SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
> > + SUN6I_DPHY_RX_TIME0_LP_RX(255));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 8));
> > +
> > + /*
> > + * The Allwinner BSP has an alternative formula for LP_RX_ULPS_WP:
> > + * lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
> > + * but does not use it and hardcodes 255 instead.
> > + */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
> > + SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
> > + SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
> > +
> > + /* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
> > + SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + lprst_dly = 4 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
> > + SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
> > +
> > + /* Analog parameters are hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> > + SUN6I_DPHY_ANA0_REG_PWS |
> > + SUN6I_DPHY_ANA0_REG_SLV(7) |
> > + SUN6I_DPHY_ANA0_REG_SFB(2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > + SUN6I_DPHY_ANA1_REG_SVTT(4));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
> > + SUN6I_DPHY_ANA4_REG_DMPLVC |
> > + SUN6I_DPHY_ANA4_REG_DMPLVD(1));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
> > + SUN6I_DPHY_ANA2_REG_ENIB);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
> > + SUN6I_DPHY_ANA3_EN_LDOR |
> > + SUN6I_DPHY_ANA3_EN_LDOC |
> > + SUN6I_DPHY_ANA3_EN_LDOD);
> > +
> > + /*
> > + * Delay comes from the Allwinner BSP, likely for internal regulator
> > + * ramp-up.
> > + */
> > + udelay(3);
> > +
> > + value = SUN6I_DPHY_RX_CTL_EN_DBC | SUN6I_DPHY_RX_CTL_RX_CLK_FORCE;
> > +
> > + /*
> > + * Rx data lane force-enable bits are used as regular RX enable by the
> > + * Allwinner BSP.
> > + */
> > + if (dphy->config.lanes >= 1)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D0_FORCE;
> > + if (dphy->config.lanes >= 2)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D1_FORCE;
> > + if (dphy->config.lanes >= 3)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D2_FORCE;
> > + if (dphy->config.lanes == 4)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D3_FORCE;
>
> I would replace this by a switch case with fallthrough to avoid too many comparisons
> to the same value.
Okay, why not!
Cheers,
Paul
> Regards,
> Helen
>
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> > + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> > + SUN6I_DPHY_GCTL_EN);
> > +
> > + return 0;
> > +}
> > +
> > +static int sun6i_dphy_power_on(struct phy *phy)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + switch (dphy->submode) {
> > + case PHY_MIPI_DPHY_SUBMODE_TX:
> > + return sun6i_dphy_tx_power_on(dphy);
> > + case PHY_MIPI_DPHY_SUBMODE_RX:
> > + return sun6i_dphy_rx_power_on(dphy);
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > static int sun6i_dphy_power_off(struct phy *phy)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> >
> > - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > - SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 0);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
> >
> > return 0;
> > }
> > @@ -234,6 +389,7 @@ static int sun6i_dphy_exit(struct phy *phy)
> >
> >
> > static const struct phy_ops sun6i_dphy_ops = {
> > + .set_mode = sun6i_dphy_set_mode,
> > .configure = sun6i_dphy_configure,
> > .power_on = sun6i_dphy_power_on,
> > .power_off = sun6i_dphy_power_off,
> >
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: Helen Koike <helen.koike@collabora.com>
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, Maxime Ripard <mripard@kernel.org>,
Chen-Yu Tsai <wens@csie.org>, Hans Verkuil <hverkuil@xs4all.nl>,
linux-sunxi@googlegroups.com, Rob Herring <robh+dt@kernel.org>,
Vinod Koul <vkoul@kernel.org>, Yong Deng <yong.deng@magewell.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Hans Verkuil <hans.verkuil@cisco.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
kevin.lhopital@hotmail.com, linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Date: Wed, 4 Nov 2020 11:54:59 +0100 [thread overview]
Message-ID: <20201104105459.GF285779@aptenodytes> (raw)
In-Reply-To: <5df82a6c-daa3-8e47-b7a4-85da60b87dd2@collabora.com>
[-- Attachment #1.1: Type: text/plain, Size: 9502 bytes --]
Hi Helen and thanks for the review,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > former, to be used with MIPI CSI-2.
> >
> > This implementation is inspired by the Allwinner BSP implementation.
> >
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > ---
> > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++++++++++++++++++-
> > 1 file changed, 160 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > index 1fa761ba6cbb..8bcd4bb79f60 100644
> > --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > @@ -24,6 +24,14 @@
> > #define SUN6I_DPHY_TX_CTL_REG 0x04
> > #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
> >
> > +#define SUN6I_DPHY_RX_CTL_REG 0x08
> > +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
> > +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
> > +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
> > +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
> > +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
> > +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
> > +
> > #define SUN6I_DPHY_TX_TIME0_REG 0x10
> > #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24)
> > #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
> > @@ -44,12 +52,29 @@
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
> >
> > +#define SUN6I_DPHY_RX_TIME0_REG 0x30
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
> > +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
> > +
> > +#define SUN6I_DPHY_RX_TIME1_REG 0x34
> > +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
> > +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xfffff)
> > +
> > +#define SUN6I_DPHY_RX_TIME2_REG 0x38
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
> > +
> > +#define SUN6I_DPHY_RX_TIME3_REG 0x40
> > +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0xffff) << 16)
> > +
> > #define SUN6I_DPHY_ANA0_REG 0x4c
> > #define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
> > #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
> > #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
> > #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
> > #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
> > +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
> >
> > #define SUN6I_DPHY_ANA1_REG 0x50
> > #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
> > @@ -92,6 +117,8 @@ struct sun6i_dphy {
> >
> > struct phy *phy;
> > struct phy_configure_opts_mipi_dphy config;
> > +
> > + int submode;
> > };
> >
> > static int sun6i_dphy_init(struct phy *phy)
> > @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_MIPI_DPHY)
> > + return -EINVAL;
> > +
> > + dphy->submode = submode;
>
> Shouldn't you check if the submode is valid here?
Yes that's a good point, thanks!
> > +
> > + return 0;
> > +}
> > +
> > static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > @@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> > return 0;
> > }
> >
> > -static int sun6i_dphy_power_on(struct phy *phy)
> > +static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> > {
> > - struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
> >
> > regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
> > @@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
> > +{
> > + /* Physical clock rate is actually half of symbol rate with DDR. */
> > + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
> > + unsigned long dphy_clk_rate;
> > + unsigned int rx_dly;
> > + unsigned int lprst_dly;
> > + u32 value;
> > +
> > + dphy_clk_rate = clk_get_rate(dphy->mod_clk);
> > + if (!dphy_clk_rate)
> > + return -1;
> > +
> > + /* Hardcoded timing parameters from the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
> > + SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
> > + SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
> > + SUN6I_DPHY_RX_TIME0_LP_RX(255));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 8));
> > +
> > + /*
> > + * The Allwinner BSP has an alternative formula for LP_RX_ULPS_WP:
> > + * lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
> > + * but does not use it and hardcodes 255 instead.
> > + */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
> > + SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
> > + SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
> > +
> > + /* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
> > + SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
> > +
> > + /*
> > + * Formula from the Allwinner BSP, with hardcoded coefficients
> > + * (probably internal divider/multiplier).
> > + */
> > + lprst_dly = 4 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
> > + SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
> > +
> > + /* Analog parameters are hardcoded in the Allwinner BSP. */
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> > + SUN6I_DPHY_ANA0_REG_PWS |
> > + SUN6I_DPHY_ANA0_REG_SLV(7) |
> > + SUN6I_DPHY_ANA0_REG_SFB(2));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > + SUN6I_DPHY_ANA1_REG_SVTT(4));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
> > + SUN6I_DPHY_ANA4_REG_DMPLVC |
> > + SUN6I_DPHY_ANA4_REG_DMPLVD(1));
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
> > + SUN6I_DPHY_ANA2_REG_ENIB);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
> > + SUN6I_DPHY_ANA3_EN_LDOR |
> > + SUN6I_DPHY_ANA3_EN_LDOC |
> > + SUN6I_DPHY_ANA3_EN_LDOD);
> > +
> > + /*
> > + * Delay comes from the Allwinner BSP, likely for internal regulator
> > + * ramp-up.
> > + */
> > + udelay(3);
> > +
> > + value = SUN6I_DPHY_RX_CTL_EN_DBC | SUN6I_DPHY_RX_CTL_RX_CLK_FORCE;
> > +
> > + /*
> > + * Rx data lane force-enable bits are used as regular RX enable by the
> > + * Allwinner BSP.
> > + */
> > + if (dphy->config.lanes >= 1)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D0_FORCE;
> > + if (dphy->config.lanes >= 2)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D1_FORCE;
> > + if (dphy->config.lanes >= 3)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D2_FORCE;
> > + if (dphy->config.lanes == 4)
> > + value |= SUN6I_DPHY_RX_CTL_RX_D3_FORCE;
>
> I would replace this by a switch case with fallthrough to avoid too many comparisons
> to the same value.
Okay, why not!
Cheers,
Paul
> Regards,
> Helen
>
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> > + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> > + SUN6I_DPHY_GCTL_EN);
> > +
> > + return 0;
> > +}
> > +
> > +static int sun6i_dphy_power_on(struct phy *phy)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + switch (dphy->submode) {
> > + case PHY_MIPI_DPHY_SUBMODE_TX:
> > + return sun6i_dphy_tx_power_on(dphy);
> > + case PHY_MIPI_DPHY_SUBMODE_RX:
> > + return sun6i_dphy_rx_power_on(dphy);
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > static int sun6i_dphy_power_off(struct phy *phy)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> >
> > - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > - SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 0);
> > +
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
> > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
> >
> > return 0;
> > }
> > @@ -234,6 +389,7 @@ static int sun6i_dphy_exit(struct phy *phy)
> >
> >
> > static const struct phy_ops sun6i_dphy_ops = {
> > + .set_mode = sun6i_dphy_set_mode,
> > .configure = sun6i_dphy_configure,
> > .power_on = sun6i_dphy_power_on,
> > .power_off = sun6i_dphy_power_off,
> >
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2020-11-04 10:55 UTC|newest]
Thread overview: 198+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 17:45 [PATCH 00/14] Allwinner MIPI CSI-2 support for A31/V3s/A83T Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 01/14] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 18:18 ` [linux-sunxi] " Jernej Škrabec
2020-10-23 18:18 ` Jernej Škrabec
2020-10-23 18:18 ` Jernej Škrabec
2020-10-24 8:31 ` Paul Kocialkowski
2020-10-24 8:31 ` Paul Kocialkowski
2020-10-24 8:31 ` Paul Kocialkowski
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-10-23 17:45 ` [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2 Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 15:38 ` Maxime Ripard
2020-10-26 15:38 ` Maxime Ripard
2020-10-26 15:38 ` Maxime Ripard
2020-10-27 9:23 ` Paul Kocialkowski
2020-10-27 9:23 ` Paul Kocialkowski
2020-10-27 9:23 ` Paul Kocialkowski
2020-10-27 18:28 ` Maxime Ripard
2020-10-27 18:28 ` Maxime Ripard
2020-10-27 18:28 ` Maxime Ripard
2020-11-04 10:53 ` Paul Kocialkowski
2020-11-04 10:53 ` Paul Kocialkowski
2020-11-04 10:53 ` Paul Kocialkowski
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-11-04 10:54 ` Paul Kocialkowski [this message]
2020-11-04 10:54 ` Paul Kocialkowski
2020-11-04 10:54 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 03/14] media: sun6i-csi: Support an optional dedicated memory pool Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 15:41 ` Maxime Ripard
2020-10-26 15:41 ` Maxime Ripard
2020-10-26 15:41 ` Maxime Ripard
2020-10-27 9:26 ` Paul Kocialkowski
2020-10-27 9:26 ` Paul Kocialkowski
2020-10-27 9:26 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 04/14] media: sun6i-csi: Fix the image storage bpp for 10/12-bit Bayer formats Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-30 22:45 ` Helen Koike
2020-10-30 22:45 ` Helen Koike
2020-10-30 22:45 ` Helen Koike
2020-11-04 10:56 ` Paul Kocialkowski
2020-11-04 10:56 ` Paul Kocialkowski
2020-11-04 10:56 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 05/14] media: sun6i-csi: Only configure the interface data width for parallel Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 16:00 ` Maxime Ripard
2020-10-26 16:00 ` Maxime Ripard
2020-10-26 16:00 ` Maxime Ripard
2020-10-27 9:31 ` Paul Kocialkowski
2020-10-27 9:31 ` Paul Kocialkowski
2020-10-27 9:31 ` Paul Kocialkowski
2020-10-27 18:31 ` Maxime Ripard
2020-10-27 18:31 ` Maxime Ripard
2020-10-27 18:31 ` Maxime Ripard
2020-10-23 17:45 ` [PATCH 06/14] media: sun6i-csi: Support feeding from the MIPI CSI-2 controller Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 07/14] dt-bindings: media: i2c: Add A31 MIPI CSI-2 bindings documentation Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 16:14 ` Maxime Ripard
2020-10-26 16:14 ` Maxime Ripard
2020-10-26 16:14 ` Maxime Ripard
2020-10-27 9:52 ` Paul Kocialkowski
2020-10-27 9:52 ` Paul Kocialkowski
2020-10-27 9:52 ` Paul Kocialkowski
2020-10-27 18:44 ` Maxime Ripard
2020-10-27 18:44 ` Maxime Ripard
2020-10-27 18:44 ` Maxime Ripard
2020-11-04 10:48 ` Paul Kocialkowski
2020-11-04 10:48 ` Paul Kocialkowski
2020-11-04 10:48 ` Paul Kocialkowski
2020-11-04 16:53 ` Maxime Ripard
2020-11-04 16:53 ` Maxime Ripard
2020-11-04 16:53 ` Maxime Ripard
2020-10-30 16:33 ` Rob Herring
2020-10-30 16:33 ` Rob Herring
2020-10-30 16:33 ` Rob Herring
2020-10-30 16:56 ` Sakari Ailus
2020-10-30 16:56 ` Sakari Ailus
2020-10-30 16:56 ` Sakari Ailus
2020-10-23 17:45 ` [PATCH 08/14] media: sunxi: Add support for the A31 MIPI CSI-2 controller Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 8:39 ` Dan Carpenter
2020-10-26 8:39 ` Dan Carpenter
2020-10-26 8:39 ` Dan Carpenter
2020-10-26 16:54 ` Maxime Ripard
2020-10-26 16:54 ` Maxime Ripard
2020-10-26 16:54 ` Maxime Ripard
2020-11-04 11:34 ` Paul Kocialkowski
2020-11-04 11:34 ` Paul Kocialkowski
2020-11-04 11:34 ` Paul Kocialkowski
2020-11-04 18:56 ` Maxime Ripard
2020-11-04 18:56 ` Maxime Ripard
2020-11-04 18:56 ` Maxime Ripard
2020-11-05 14:52 ` Paul Kocialkowski
2020-11-05 14:52 ` Paul Kocialkowski
2020-11-05 14:52 ` Paul Kocialkowski
2020-10-30 22:45 ` Helen Koike
2020-10-30 22:45 ` Helen Koike
2020-10-30 22:45 ` Helen Koike
2020-11-02 9:21 ` Maxime Ripard
2020-11-02 9:21 ` Maxime Ripard
2020-11-02 9:21 ` Maxime Ripard
2020-11-04 11:17 ` Paul Kocialkowski
2020-11-04 11:17 ` Paul Kocialkowski
2020-11-04 11:17 ` Paul Kocialkowski
2020-11-04 16:38 ` Helen Koike
2020-11-04 16:38 ` Helen Koike
2020-11-04 16:38 ` Helen Koike
2020-11-04 18:45 ` Maxime Ripard
2020-11-04 18:45 ` Maxime Ripard
2020-11-04 18:45 ` Maxime Ripard
2020-11-05 14:14 ` Helen Koike
2020-11-05 14:14 ` Helen Koike
2020-11-05 14:14 ` Helen Koike
2020-11-05 8:45 ` Sakari Ailus
2020-11-05 8:45 ` Sakari Ailus
2020-11-05 8:45 ` Sakari Ailus
2020-11-05 14:55 ` Paul Kocialkowski
2020-11-05 14:55 ` Paul Kocialkowski
2020-11-05 14:55 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 09/14] ARM: dts: sun8i: v3s: Add CSI0 camera interface node Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 10/14] ARM: dts: sun8i: v3s: Add MIPI D-PHY and MIPI CSI-2 interface nodes Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 16:55 ` Maxime Ripard
2020-10-26 16:55 ` Maxime Ripard
2020-10-26 16:55 ` Maxime Ripard
2020-10-23 17:45 ` [PATCH 11/14] dt-bindings: media: i2c: Add A83T MIPI CSI-2 bindings documentation Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 16:56 ` Maxime Ripard
2020-10-26 16:56 ` Maxime Ripard
2020-10-26 16:56 ` Maxime Ripard
2020-11-04 10:33 ` Paul Kocialkowski
2020-11-04 10:33 ` Paul Kocialkowski
2020-11-04 10:33 ` Paul Kocialkowski
2020-11-05 8:48 ` Sakari Ailus
2020-11-05 8:48 ` Sakari Ailus
2020-11-05 8:48 ` Sakari Ailus
2020-10-23 17:45 ` [PATCH 12/14] media: sunxi: Add support for the A83T MIPI CSI-2 controller Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 8:53 ` Dan Carpenter
2020-10-26 8:53 ` Dan Carpenter
2020-10-26 8:53 ` Dan Carpenter
2020-10-26 17:00 ` Maxime Ripard
2020-10-26 17:00 ` Maxime Ripard
2020-10-26 17:00 ` Maxime Ripard
2020-11-04 10:37 ` Paul Kocialkowski
2020-11-04 10:37 ` Paul Kocialkowski
2020-11-04 10:37 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 13/14] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` [PATCH 14/14] media: sunxi: sun8i-a83t-mipi-csi2: Avoid using the (unsolicited) interrupt Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-23 17:45 ` Paul Kocialkowski
2020-10-26 16:57 ` Maxime Ripard
2020-10-26 16:57 ` Maxime Ripard
2020-10-26 16:57 ` Maxime Ripard
2020-10-26 17:20 ` [PATCH 00/14] Allwinner MIPI CSI-2 support for A31/V3s/A83T Maxime Ripard
2020-10-26 17:20 ` Maxime Ripard
2020-10-26 17:20 ` Maxime Ripard
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-10-30 22:44 ` Helen Koike
2020-11-02 9:17 ` Maxime Ripard
2020-11-02 9:17 ` Maxime Ripard
2020-11-02 9:17 ` Maxime Ripard
2020-11-04 11:11 ` Paul Kocialkowski
2020-11-04 11:11 ` Paul Kocialkowski
2020-11-04 11:11 ` Paul Kocialkowski
2020-11-04 11:14 ` Paul Kocialkowski
2020-11-04 11:14 ` Paul Kocialkowski
2020-11-04 11:14 ` Paul Kocialkowski
2020-11-04 16:36 ` Helen Koike
2020-11-04 16:36 ` Helen Koike
2020-11-04 16:36 ` Helen Koike
2020-11-05 14:58 ` Paul Kocialkowski
2020-11-05 14:58 ` Paul Kocialkowski
2020-11-05 14:58 ` Paul Kocialkowski
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