From: Peter Geis <pgwipeout@gmail.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, Prashant Gaikwad <pgaikwad@nvidia.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>, Sameer Pujar <spujar@nvidia.com>, Mohan Kumar <mkumard@nvidia.com> Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Peter Geis <pgwipeout@gmail.com>, Ion Agorria <ion@agorria.com> Subject: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver Date: Fri, 8 Jan 2021 13:59:12 +0000 [thread overview] Message-ID: <20210108135913.2421585-2-pgwipeout@gmail.com> (raw) In-Reply-To: <20210108135913.2421585-1-pgwipeout@gmail.com> Current implementation defaults the hda clocks to clk_m. This causes hda to run too slow to operate correctly. Fix this by defaulting to pll_p and setting the frequency to the correct rate. This matches upstream t124 and downstream t30. Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- drivers/clk/tegra/clk-tegra30.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..9cf249c344d9 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Peter Geis <pgwipeout@gmail.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, Prashant Gaikwad <pgaikwad@nvidia.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>, Sameer Pujar <spujar@nvidia.com>, Mohan Kumar <mkumard@nvidia.com> Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Ion Agorria <ion@agorria.com>, Peter Geis <pgwipeout@gmail.com>, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver Date: Fri, 8 Jan 2021 13:59:12 +0000 [thread overview] Message-ID: <20210108135913.2421585-2-pgwipeout@gmail.com> (raw) In-Reply-To: <20210108135913.2421585-1-pgwipeout@gmail.com> Current implementation defaults the hda clocks to clk_m. This causes hda to run too slow to operate correctly. Fix this by defaulting to pll_p and setting the frequency to the correct rate. This matches upstream t124 and downstream t30. Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- drivers/clk/tegra/clk-tegra30.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..9cf249c344d9 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; -- 2.25.1
next prev parent reply other threads:[~2021-01-08 14:00 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-08 13:59 [PATCH v2 0/2] fix tegra-hda on tegra30 devices Peter Geis 2021-01-08 13:59 ` Peter Geis 2021-01-08 13:59 ` Peter Geis [this message] 2021-01-08 13:59 ` [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver Peter Geis 2021-01-08 15:13 ` Sameer Pujar 2021-01-08 15:13 ` Sameer Pujar 2021-01-12 12:58 ` Thierry Reding 2021-01-12 12:58 ` Thierry Reding 2021-01-08 13:59 ` [PATCH v2 2/2] ALSA: hda/tegra: fix tegra-hda on tegra30 soc Peter Geis 2021-01-08 13:59 ` Peter Geis 2021-01-08 15:15 ` Sameer Pujar 2021-01-08 15:15 ` Sameer Pujar 2021-01-12 12:58 ` Thierry Reding 2021-01-12 12:58 ` Thierry Reding 2021-01-12 8:22 ` [PATCH v2 0/2] fix tegra-hda on tegra30 devices Takashi Iwai 2021-01-12 8:22 ` Takashi Iwai 2021-01-12 13:00 ` Thierry Reding 2021-01-12 13:00 ` Thierry Reding 2021-01-12 13:46 ` Takashi Iwai 2021-01-12 13:46 ` Takashi Iwai
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